license: remove FSF postal address from boiler plate license text

[libsigrokdecode.git] / decoders / usb_signalling / pd.py

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index 8225ae7cb9e4bdb7191ca8b61c76c179bc76ae71..0ad8fdc707d53c6dead64d65200268abbe37f0c1 100644 (file)
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -15,8 +15,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -69,10 +68,11 @@ symbols = {
         (0, 1): 'LS_J',
         (1, 1): 'SE1',
     },
-# After a PREamble PID, the bus segment between Host and Hub uses LS signalling
-# rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For both upstream and
-# downstream low-speed data, the hub is responsible for inverting the polarity of
-# the data before transmitting to/from a low-speed port."
+    # After a PREamble PID, the bus segment between Host and Hub uses LS
+    # signalling rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For
+    # both upstream and downstream low-speed data, the hub is responsible for
+    # inverting the polarity of the data before transmitting to/from a
+    # low-speed port.").
     'low-speed-rp': {
         # (<dp>, <dm>): <symbol/state>
         (0, 0): 'SE0',
@@ -83,8 +83,8 @@ symbols = {
 }
 
 bitrates = {
-    'low-speed': 1500000,   # 1.5Mb/s (+/- 1.5%)
-    'low-speed-rp': 1500000,   # 1.5Mb/s (+/- 1.5%)
+    'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
+    'low-speed-rp': 1500000, # 1.5Mb/s (+/- 1.5%)
     'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
     'automatic': None
 }
@@ -148,6 +148,7 @@ class Decoder(srd.Decoder):
         self.oldpins = None
         self.edgepins = None
         self.consecutive_ones = 0
+        self.bits = None
         self.state = 'INIT'
 
     def start(self):
@@ -200,6 +201,7 @@ class Decoder(srd.Decoder):
         if sym != 'K' or self.oldsym != 'J':
             return
         self.consecutive_ones = 0
+        self.bits = ''
         self.update_bitrate()
         self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
         self.set_new_target_samplenum()
@@ -247,16 +249,26 @@ class Decoder(srd.Decoder):
 
     def get_bit(self, sym):
         self.set_new_target_samplenum()
+        b = '0' if self.oldsym != sym else '1'
+        self.oldsym = sym
         if sym == 'SE0':
             # Start of an EOP. Change state, save edge
             self.state = 'GET EOP'
             self.ss_block = self.samplenum_lastedge
         else:
-            b = '0' if self.oldsym != sym else '1'
             self.handle_bit(b)
         self.putpb(['SYM', sym])
         self.putb(sym_annotation[sym])
-        if self.oldsym != sym:
+        if len(self.bits) <= 16:
+            self.bits += b
+        if len(self.bits) == 16 and self.bits == '0000000100111100':
+            # Sync and low-speed PREamble seen
+            self.putpx(['EOP', None])
+            self.state = 'IDLE'
+            self.signalling = 'low-speed-rp'
+            self.update_bitrate()
+            self.oldsym = 'J'
+        if b == '0':
             edgesym = symbols[self.signalling][tuple(self.edgepins)]
             if edgesym not in ('SE0', 'SE1'):
                 if edgesym == sym:
@@ -265,7 +277,6 @@ class Decoder(srd.Decoder):
                 else:
                     self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
                     self.samplepos = self.samplepos + (0.01 * self.bitwidth)
-        self.oldsym = sym
 
     def handle_idle(self, sym):
         self.samplenum_edge = self.samplenum