srd: rename extra_probes to optional_probes in all PDs

[libsigrokdecode.git] / decoders / uart / uart.py

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index f827a22d8a3d26b999e76f70b2c82f5906f0337b..b70496fc650e14e30494327e4e00af84a8342553 100644 (file)
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -173,13 +173,13 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits):
         return parity_bit == 1
 
     # Count number of 1 (high) bits in the data (and the parity bit itself!).
-    parity = bin(data).count('1') + parity_bit
+    ones = bin(data).count('1') + parity_bit
 
     # Check for odd/even parity.
     if parity_type == PARITY_ODD:
-        return (parity % 2) == 1
+        return (ones % 2) == 1
     elif parity_type == PARITY_EVEN:
-        return (parity % 2) == 0
+        return (ones % 2) == 0
     else:
         raise Exception('Invalid parity type: %d' % parity_type)
 
@@ -199,11 +199,12 @@ class Decoder(srd.Decoder):
         {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
         {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
     ]
+    optional_probes = []
     options = {
         'baudrate': ['Baud rate', 115200],
         'num_data_bits': ['Data bits', 8], # Valid: 5-9.
-        'parity': ['Parity', PARITY_NONE], # TODO: Rename to parity_type.
-        'parity_check': ['Check parity', True], # TODO: Bool supported?
+        'parity_type': ['Parity type', PARITY_NONE],
+        'parity_check': ['Check parity?', True], # TODO: Bool supported?
         'num_stop_bits': ['Stop bit(s)', STOP_BITS_1],
         'bit_order': ['Bit order', LSB_FIRST],
         # TODO: Options to invert the signal(s).
@@ -309,7 +310,8 @@ class Decoder(srd.Decoder):
         # Get the next data bit in LSB-first or MSB-first fashion.
         if self.options['bit_order'] == LSB_FIRST:
             self.databyte[rxtx] >>= 1
-            self.databyte[rxtx] |= (signal << (self.options['num_data_bits'] - 1))
+            self.databyte[rxtx] |= \
+                (signal << (self.options['num_data_bits'] - 1))
         elif self.options['bit_order'] == MSB_FIRST:
             self.databyte[rxtx] <<= 1
             self.databyte[rxtx] |= (signal << 0)
@@ -340,7 +342,7 @@ class Decoder(srd.Decoder):
 
     def get_parity_bit(self, rxtx, signal):
         # If no parity is used/configured, skip to the next state immediately.
-        if self.options['parity'] == PARITY_NONE:
+        if self.options['parity_type'] == PARITY_NONE:
             self.state[rxtx] = GET_STOP_BITS
             return
 
@@ -352,7 +354,7 @@ class Decoder(srd.Decoder):
 
         self.state[rxtx] = GET_STOP_BITS
 
-        if parity_ok(self.options['parity'], self.paritybit[rxtx],
+        if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
                      self.databyte[rxtx], self.options['num_data_bits']):
             # TODO: Fix range.
             self.put(self.samplenum, self.samplenum, self.out_proto,
@@ -370,7 +372,7 @@ class Decoder(srd.Decoder):
     # TODO: Currently only supports 1 stop bit.
     def get_stop_bits(self, rxtx, signal):
         # Skip samples until we're in the middle of the stop bit(s).
-        skip_parity = 0 if self.options['parity'] == PARITY_NONE else 1
+        skip_parity = 0 if self.options['parity_type'] == PARITY_NONE else 1
         b = self.options['num_data_bits'] + 1 + skip_parity
         if not self.reached_bit(rxtx, b):
             return
@@ -391,7 +393,8 @@ class Decoder(srd.Decoder):
         self.put(self.samplenum, self.samplenum, self.out_ann,
                  [ANN_ASCII, ['Stop bit', 'Stop', 'P']])
 
-    def decode(self, ss, es, data): # TODO
+    def decode(self, ss, es, data):
+        # TODO: Either RX or TX could be omitted (optional probe).
         for (samplenum, (rx, tx)) in data:
 
             # TODO: Start counting at 0 or 1? Increase before or after?
@@ -420,7 +423,7 @@ class Decoder(srd.Decoder):
                 elif self.state[rxtx] == GET_STOP_BITS:
                     self.get_stop_bits(rxtx, signal)
                 else:
-                    raise Exception('Invalid state: %s' % self.state[rxtx])
+                    raise Exception('Invalid state: %d' % self.state[rxtx])
 
                 # Save current RX/TX values for the next round.
                 self.oldbit[rxtx] = signal