srd: rename extra_probes to optional_probes in all PDs

[libsigrokdecode.git] / decoders / uart / uart.py

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index 7cefe740bff73d389bc6d1dbe4a5155f35ce957f..b70496fc650e14e30494327e4e00af84a8342553 100644 (file)
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -199,7 +199,7 @@ class Decoder(srd.Decoder):
         {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
         {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
     ]
         {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
         {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
     ]

-    extra_probes = []
+    optional_probes = []

     options = {
         'baudrate': ['Baud rate', 115200],
         'num_data_bits': ['Data bits', 8], # Valid: 5-9.
     options = {
         'baudrate': ['Baud rate', 115200],
         'num_data_bits': ['Data bits', 8], # Valid: 5-9.


@@ -310,7 +310,8 @@ class Decoder(srd.Decoder):
         # Get the next data bit in LSB-first or MSB-first fashion.
         if self.options['bit_order'] == LSB_FIRST:
             self.databyte[rxtx] >>= 1
         # Get the next data bit in LSB-first or MSB-first fashion.
         if self.options['bit_order'] == LSB_FIRST:
             self.databyte[rxtx] >>= 1

-            self.databyte[rxtx] |= (signal << (self.options['num_data_bits'] - 1))
+            self.databyte[rxtx] |= \
+                (signal << (self.options['num_data_bits'] - 1))

         elif self.options['bit_order'] == MSB_FIRST:
             self.databyte[rxtx] <<= 1
             self.databyte[rxtx] |= (signal << 0)
         elif self.options['bit_order'] == MSB_FIRST:
             self.databyte[rxtx] <<= 1
             self.databyte[rxtx] |= (signal << 0)