- 'STARTBIT': The data is the (integer) value of the start bit (0/1).
- 'DATA': The data is the (integer) value of the UART data. Valid values
range from 0 to 512 (as the data can be up to 9 bits in size).
+ - 'DATABITS': List of data bits and their ss/es numbers.
- 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
- 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
- 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
{'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
{'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
]
- options = {
- 'baudrate': ['Baud rate', 115200],
- 'num_data_bits': ['Data bits', 8], # Valid: 5-9.
- 'parity_type': ['Parity type', 'none'],
- 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
- 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
- 'bit_order': ['Bit order', 'lsb-first'],
- 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin
+ options = (
+ {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
+ {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8,
+ 'values': (5, 6, 7, 8, 9)},
+ {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none',
+ 'values': ('none', 'odd', 'even', 'zero', 'one')},
+ {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes',
+ 'values': ('yes', 'no')},
+ {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0,
+ 'values': (0.0, 0.5, 1.0, 1.5)},
+ {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
+ 'values': ('lsb-first', 'msb-first')},
+ {'id': 'format', 'desc': 'Data format', 'default': 'ascii',
+ 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
# TODO: Options to invert the signal(s).
- }
+ )
annotations = [
- ['rx-data', 'UART RX data'],
- ['tx-data', 'UART TX data'],
- ['start-bits', 'UART start bits'],
- ['parity-bits', 'UART parity bits'],
- ['stop-bits', 'UART stop bits'],
- ['warnings', 'Warnings'],
+ ['rx-data', 'RX data'],
+ ['tx-data', 'TX data'],
+ ['rx-start', 'RX start bits'],
+ ['tx-start', 'TX start bits'],
+ ['rx-parity-ok', 'RX parity OK bits'],
+ ['tx-parity-ok', 'TX parity OK bits'],
+ ['rx-parity-err', 'RX parity error bits'],
+ ['tx-parity-err', 'TX parity error bits'],
+ ['rx-stop', 'RX stop bits'],
+ ['tx-stop', 'TX stop bits'],
+ ['rx-warnings', 'RX warnings'],
+ ['tx-warnings', 'TX warnings'],
+ ['rx-data-bits', 'RX data bits'],
+ ['tx-data-bits', 'TX data bits'],
]
+ annotation_rows = (
+ ('rx-data', 'RX', (0, 2, 4, 6, 8)),
+ ('rx-data-bits', 'RX bits', (12,)),
+ ('rx-warnings', 'RX warnings', (10,)),
+ ('tx-data', 'TX', (1, 3, 5, 7, 9)),
+ ('tx-data-bits', 'TX bits', (13,)),
+ ('tx-warnings', 'TX warnings', (11,)),
+ )
binary = (
('rx', 'RX dump'),
('tx', 'TX dump'),
s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data)
+ def putpx(self, rxtx, data):
+ s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
+ self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data)
+
def putg(self, data):
s, halfbit = self.samplenum, int(self.bit_width / 2)
self.put(s - halfbit, s + halfbit, self.out_ann, data)
self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
self.oldbit = [1, 1]
self.oldpins = [1, 1]
+ self.databits = [[], []]
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.state[rxtx] = 'GET DATA BITS'
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([2, ['Start bit', 'Start', 'S']])
+ self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
def get_data_bits(self, rxtx, signal):
# Skip samples until we're in the middle of the desired data bit.
raise Exception('Invalid bit order value: %s',
self.options['bit_order'])
+ self.putg([rxtx + 12, ['%d' % signal]])
+
+ # Store individual data bits and their start/end samplenumbers.
+ s, halfbit = self.samplenum, int(self.bit_width / 2)
+ self.databits[rxtx].append([signal, s - halfbit, s + halfbit])
+
# Return here, unless we already received all data bits.
if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
self.cur_data_bit[rxtx] += 1
self.state[rxtx] = 'GET PARITY BIT'
- self.putp(['DATA', rxtx, self.databyte[rxtx]])
+ self.putpx(rxtx, ['DATABITS', rxtx, self.databits[rxtx]])
+ self.putpx(rxtx, ['DATA', rxtx, self.databyte[rxtx]])
b, f = self.databyte[rxtx], self.options['format']
if f == 'ascii':
self.putbin(rxtx, (rxtx, bytes([b])))
self.putbin(rxtx, (2, bytes([b])))
+ self.databits = [[], []]
+
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.
if self.options['parity_type'] == 'none':
if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
self.databyte[rxtx], self.options['num_data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([3, ['Parity bit', 'Parity', 'P']])
+ self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([5, ['Parity error', 'Parity err', 'PE']])
+ self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([5, ['Frame error', 'Frame err', 'FE']])
+ self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
self.state[rxtx] = 'WAIT FOR START BIT'
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([4, ['Stop bit', 'Stop', 'T']])
+ self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
def decode(self, ss, es, data):
if self.samplerate is None:
projects / libsigrokdecode.git / blobdiff