## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# UART protocol decoder
-
import sigrokdecode as srd
'''
-Protocol output format:
+OUTPUT_PYTHON format:
-UART packet:
-[<packet-type>, <rxtx>, <packet-data>]
+Packet:
+[<ptype>, <rxtx>, <pdata>]
-This is the list of <packet-type>s and their respective <packet-data>:
+This is the list of <ptype>s and their respective <pdata> values:
- 'STARTBIT': The data is the (integer) value of the start bit (0/1).
- 'DATA': The data is the (integer) value of the UART data. Valid values
range from 0 to 512 (as the data can be up to 9 bits in size).
+ - 'DATABITS': List of data bits and their ss/es numbers.
- 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
- 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
- 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
return (ones % 2) == 1
elif parity_type == 'even':
return (ones % 2) == 0
- else:
- raise Exception('Invalid parity type: %d' % parity_type)
+
+class SamplerateError(Exception):
+ pass
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 2
id = 'uart'
name = 'UART'
longname = 'Universal Asynchronous Receiver/Transmitter'
license = 'gplv2+'
inputs = ['logic']
outputs = ['uart']
- probes = [
+ optional_channels = (
# Allow specifying only one of the signals, e.g. if only one data
# direction exists (or is relevant).
{'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
{'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
- ]
- optional_probes = []
- options = {
- 'baudrate': ['Baud rate', 115200],
- 'num_data_bits': ['Data bits', 8], # Valid: 5-9.
- 'parity_type': ['Parity type', 'none'],
- 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
- 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
- 'bit_order': ['Bit order', 'lsb-first'],
- 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin
+ )
+ options = (
+ {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
+ {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8,
+ 'values': (5, 6, 7, 8, 9)},
+ {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none',
+ 'values': ('none', 'odd', 'even', 'zero', 'one')},
+ {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes',
+ 'values': ('yes', 'no')},
+ {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0,
+ 'values': (0.0, 0.5, 1.0, 1.5)},
+ {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
+ 'values': ('lsb-first', 'msb-first')},
+ {'id': 'format', 'desc': 'Data format', 'default': 'ascii',
+ 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
# TODO: Options to invert the signal(s).
- }
- annotations = [
- ['RX data', 'UART RX data'],
- ['TX data', 'UART TX data'],
- ['Start bits', 'UART start bits'],
- ['Parity bits', 'UART parity bits'],
- ['Stop bits', 'UART stop bits'],
- ['Warnings', 'Warnings'],
- ]
+ )
+ annotations = (
+ ('rx-data', 'RX data'),
+ ('tx-data', 'TX data'),
+ ('rx-start', 'RX start bits'),
+ ('tx-start', 'TX start bits'),
+ ('rx-parity-ok', 'RX parity OK bits'),
+ ('tx-parity-ok', 'TX parity OK bits'),
+ ('rx-parity-err', 'RX parity error bits'),
+ ('tx-parity-err', 'TX parity error bits'),
+ ('rx-stop', 'RX stop bits'),
+ ('tx-stop', 'TX stop bits'),
+ ('rx-warnings', 'RX warnings'),
+ ('tx-warnings', 'TX warnings'),
+ ('rx-data-bits', 'RX data bits'),
+ ('tx-data-bits', 'TX data bits'),
+ )
+ annotation_rows = (
+ ('rx-data', 'RX', (0, 2, 4, 6, 8)),
+ ('rx-data-bits', 'RX bits', (12,)),
+ ('rx-warnings', 'RX warnings', (10,)),
+ ('tx-data', 'TX', (1, 3, 5, 7, 9)),
+ ('tx-data-bits', 'TX bits', (13,)),
+ ('tx-warnings', 'TX warnings', (11,)),
+ )
binary = (
('rx', 'RX dump'),
('tx', 'TX dump'),
s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data)
+ def putpx(self, rxtx, data):
+ s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
+ self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data)
+
def putg(self, data):
s, halfbit = self.samplenum, int(self.bit_width / 2)
self.put(s - halfbit, s + halfbit, self.out_ann, data)
def putp(self, data):
s, halfbit = self.samplenum, int(self.bit_width / 2)
- self.put(s - halfbit, s + halfbit, self.out_proto, data)
+ self.put(s - halfbit, s + halfbit, self.out_python, data)
def putbin(self, rxtx, data):
s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
self.oldbit = [1, 1]
self.oldpins = [1, 1]
+ self.databits = [[], []]
def start(self):
- self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_bin = self.register(srd.OUTPUT_BINARY)
self.out_ann = self.register(srd.OUTPUT_ANN)
self.state[rxtx] = 'GET DATA BITS'
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([2, ['Start bit', 'Start', 'S']])
+ self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
def get_data_bits(self, rxtx, signal):
# Skip samples until we're in the middle of the desired data bit.
self.databyte[rxtx] >>= 1
self.databyte[rxtx] |= \
(signal << (self.options['num_data_bits'] - 1))
- elif self.options['bit_order'] == 'msb-first':
+ else:
self.databyte[rxtx] <<= 1
self.databyte[rxtx] |= (signal << 0)
- else:
- raise Exception('Invalid bit order value: %s',
- self.options['bit_order'])
+
+ self.putg([rxtx + 12, ['%d' % signal]])
+
+ # Store individual data bits and their start/end samplenumbers.
+ s, halfbit = self.samplenum, int(self.bit_width / 2)
+ self.databits[rxtx].append([signal, s - halfbit, s + halfbit])
# Return here, unless we already received all data bits.
if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
self.state[rxtx] = 'GET PARITY BIT'
- self.putp(['DATA', rxtx, self.databyte[rxtx]])
+ self.putpx(rxtx, ['DATABITS', rxtx, self.databits[rxtx]])
+ self.putpx(rxtx, ['DATA', rxtx, self.databyte[rxtx]])
b, f = self.databyte[rxtx], self.options['format']
if f == 'ascii':
- c = chr(b) if chr(b).isprintable() else '[%02X]' % b
+ c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b
self.putx(rxtx, [rxtx, [c]])
elif f == 'dec':
self.putx(rxtx, [rxtx, [str(b)]])
self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
elif f == 'bin':
self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
- else:
- raise Exception('Invalid data format option: %s' % f)
self.putbin(rxtx, (rxtx, bytes([b])))
self.putbin(rxtx, (2, bytes([b])))
+ self.databits = [[], []]
+
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.
if self.options['parity_type'] == 'none':
if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
self.databyte[rxtx], self.options['num_data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([3, ['Parity bit', 'Parity', 'P']])
+ self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([5, ['Parity error', 'Parity err', 'PE']])
+ self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([5, ['Frame error', 'Frame err', 'FE']])
+ self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
self.state[rxtx] = 'WAIT FOR START BIT'
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([4, ['Stop bit', 'Stop', 'T']])
+ self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
def decode(self, ss, es, data):
- if self.samplerate is None:
- raise Exception("Cannot decode without samplerate.")
- # TODO: Either RX or TX could be omitted (optional probe).
+ if not self.samplerate:
+ raise SamplerateError('Cannot decode without samplerate.')
for (self.samplenum, pins) in data:
# Note: Ignoring identical samples here for performance reasons
# continue
self.oldpins, (rx, tx) = pins, pins
+ # Either RX or TX (but not both) can be omitted.
+ has_pin = [rx in (0, 1), tx in (0, 1)]
+ if has_pin == [False, False]:
+ raise Exception('Either TX or RX (or both) pins required.')
+
# State machine.
for rxtx in (RX, TX):
+ # Don't try to handle RX (or TX) if not supplied.
+ if not has_pin[rxtx]:
+ continue
+
signal = rx if (rxtx == RX) else tx
if self.state[rxtx] == 'WAIT FOR START BIT':
self.get_parity_bit(rxtx, signal)
elif self.state[rxtx] == 'GET STOP BITS':
self.get_stop_bits(rxtx, signal)
- else:
- raise Exception('Invalid state: %s' % self.state[rxtx])
# Save current RX/TX values for the next round.
self.oldbit[rxtx] = signal
projects / libsigrokdecode.git / blobdiff