avr_isp: Add more parts

[libsigrokdecode.git] / decoders / tlc5620 / pd.py

diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 3ca1415dd7ab845f16cd798eccd3533b15632cad..8ff30d760308043fa4dd15f3c92863bfec52d6e6 100644 (file)
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -18,6 +18,9 @@
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
+
+Pin = SrdIntEnum.from_str('Pin', 'CLK DATA LOAD LDAC')
 
 dacs = {
     0: 'DACA',
@@ -34,7 +37,8 @@ class Decoder(srd.Decoder):
     desc = 'Texas Instruments TLC5620 8-bit quad DAC.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['tlc5620']
+    outputs = []
+    tags = ['IC', 'Analog/digital']
     channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
         {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
@@ -71,6 +75,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.bits = []
         self.ss_dac_first = None
         self.ss_dac = self.es_dac = 0
@@ -193,7 +200,7 @@ class Decoder(srd.Decoder):
             #   a) Falling edge on CLK, and/or
             #   b) Falling edge on LOAD, and/or
             #   b) Falling edge on LDAC
-            pins = self.wait([{0: 'f'}, {2: 'f'}, {3: 'f'}])
+            pins = self.wait([{Pin.CLK: 'f'}, {Pin.LOAD: 'f'}, {Pin.LDAC: 'f'}])
             self.ldac = pins[3]
 
             # Handle those conditions (one or more) that matched this time.