license: remove FSF postal address from boiler plate license text

[libsigrokdecode.git] / decoders / swd / pd.py

diff --git a/decoders/swd/pd.py b/decoders/swd/pd.py
index f2abf1f105ef0346164d048b146f56ae41906be0..22aad4533d25b89aba66f55edabbd4058b195156 100644 (file)
--- a/decoders/swd/pd.py
+++ b/decoders/swd/pd.py
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -65,7 +64,7 @@ BIT_CTRLSTAT_ORUNDETECT = 1
 ANNOTATIONS = ['reset', 'enable', 'read', 'write', 'ack', 'data', 'parity']
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'swd'
     name = 'SWD'
     longname = 'Serial Wire Debug'
@@ -92,10 +91,9 @@ class Decoder(srd.Decoder):
         ('parity', 'PARITY'),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         # SWD data/clock state
         self.state = 'UNKNOWN'
-        self.oldclk = -1
         self.sample_edge = RISING
         self.ack = None # Ack state of the current phase
         self.ss_req = 0 # Start sample of current req
@@ -142,11 +140,10 @@ class Decoder(srd.Decoder):
         }[(self.apdp, self.rw)]
         self.putp(ptype, (self.addr, self.data, self.ack))
 
-    def decode(self, ss, es, data):
-        for (self.samplenum, (clk, dio)) in data:
-            if clk == self.oldclk:
-                continue # Not a clock edge.
-            self.oldclk = clk
+    def decode(self):
+        while True:
+            # Wait for any clock edge.
+            clk, dio = self.wait({0: 'e'})
 
             # Count rising edges with DIO held high,
             # as a line reset (50+ high edges) can happen from any state.
@@ -340,7 +337,7 @@ class Decoder(srd.Decoder):
                 }[self.addr]
         elif self.apdp == 'AP':
             if self.rw == 'R':
-                return 'W AP%x' % self.addr
+                return 'R AP%x' % self.addr
             elif self.rw == 'W':
                 return 'W AP%x' % self.addr