srd: Finish consistency rename to ANN/PROTO.

[libsigrokdecode.git] / decoders / srd_usb.py

diff --git a/decoders/srd_usb.py b/decoders/srd_usb.py
index 128b337e50b83ee8c724ce5e3c9daa4ae0b0eeb5..c97ef730ea80e9f100cb21ab783740c9600be941 100644 (file)
--- a/decoders/srd_usb.py
+++ b/decoders/srd_usb.py
@@ -40,26 +40,15 @@
 # http://www.usb.org/developers/docs/
 #
 
-import sigrok
-
-class Sample():
-    def __init__(self, data):
-        self.data = data
-    def probe(self, probe):
-        s = ord(self.data[probe / 8]) & (1 << (probe % 8))
-        return True if s else False
-
-def sampleiter(data, unitsize):
-    for i in range(0, len(data), unitsize):
-        yield(Sample(data[i:i+unitsize]))
+import sigrokdecode
 
 # States
 SE0, J, K, SE1 = 0, 1, 2, 3
 syms = {
-        (False, False): SE0,
-        (True, False): J,
-        (False, True): K,
-        (True, True): SE1,
+        (0, 0): SE0,
+        (1, 0): J,
+        (0, 1): K,
+        (1, 1): SE1,
 }
 
 def bitstr_to_num(bitstr):
@@ -110,7 +99,8 @@ def packet_decode(packet):
 
     return pid + ' ' + data
 
-class Decoder():
+class Decoder(sigrokdecode.Decoder):
+    id = 'usb'
     name = 'USB'
     desc = 'Universal Serial Bus'
     longname = '...longname...'
@@ -121,15 +111,20 @@ class Decoder():
     inputs = ['logic']
     outputs = ['usb']
     # Probe names with a set of defaults
-    probes = {'dp':0, 'dm':1}
+    probes = [
+        {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
+        {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
+    ]
     options = {}
 
     def __init__(self):
-        self.probes = Decoder.probes.copy()
+        self.out_proto = None
+        self.out_ann = None
 
     def start(self, metadata):
-        self.unitsize = metadata['unitsize']
         self.rate = metadata['samplerate']
+        # self.out_proto = self.add(sigrokdecode.SRD_OUTPUT_PROTO, 'usb')
+        self.out_ann = self.add(sigrokdecode.SRD_OUTPUT_ANN, 'usb')
         if self.rate < 48000000:
             raise Exception("Sample rate not sufficient for USB decoding")
         # Initialise decoder state.
@@ -137,13 +132,15 @@ class Decoder():
         self.scount = 0
         self.packet = ''
 
-    def decode(self, data):
-        for sample in sampleiter(data['data'], self.unitsize):
+    def decode(self, timeoffset, duration, data):
+        out = []
+
+        # FIXME
+        for (samplenum, (dp, dm, x, y, z, a)) in data:
 
             self.scount += 1
 
-            sym = syms[sample.probe(self.probes['dp']),
-                       sample.probe(self.probes['dm'])]
+            sym = syms[dp, dm]
             if sym == self.sym:
                 continue
 
@@ -156,18 +153,18 @@ class Decoder():
 
             # How many bits since the last transition?
             if self.packet or self.sym != J:
-                bitcount = (self.scount - 1) * 12000000 / self.rate
+                bitcount = int((self.scount - 1) * 12000000 / self.rate)
             else:
                 bitcount = 0
 
             if self.sym == SE0:
                 if bitcount == 1:
                     # End-Of-Packet (EOP)
-                    sigrok.put({"type":"usb", "data":self.packet,
-                                "display":packet_decode(self.packet)})
+                    out += [{"type":"usb", "data":self.packet,
+                              "display":packet_decode(self.packet)}]
                 else:
                     # Longer than EOP, assume reset.
-                    sigrok.put({"type":"usb", "display":"RESET"})
+                    out += [{"type":"usb", "display":"RESET"}]
                 self.scount = 0
                 self.sym = sym
                 self.packet = ''
@@ -179,8 +176,12 @@ class Decoder():
             if bitcount < 6 and sym != SE0:
                 self.packet += '0'
             elif bitcount > 6:
-                sigrok.put({"type":"usb", "display":"BIT STUFF ERROR"})
+                out += [{"type":"usb", "display":"BIT STUFF ERROR"}]
 
             self.scount = 0
             self.sym = sym
 
+        if out != []:
+            # self.put(0, 0, self.out_proto, out_proto)
+            self.put(0, 0, self.out_ann, out)
+