srd: Drop useless out_ann/out_proto init.

[libsigrokdecode.git] / decoders / srd_usb.py

diff --git a/decoders/srd_usb.py b/decoders/srd_usb.py
index a223dbbade809f642355e4f60eed264769d8ed7e..c6e6627c3d4fbd47ee4becda5fd910185825894e 100644 (file)
--- a/decoders/srd_usb.py
+++ b/decoders/srd_usb.py
@@ -40,26 +40,15 @@
 # http://www.usb.org/developers/docs/
 #
 
-import sigrok
-
-class Sample():
-    def __init__(self, data):
-        self.data = data
-    def probe(self, probe):
-        s = ord(self.data[int(probe / 8)]) & (1 << (probe % 8))
-        return True if s else False
-
-def sampleiter(data, unitsize):
-    for i in range(0, len(data), unitsize):
-        yield(Sample(data[i:i+unitsize]))
+import sigrokdecode as srd
 
 # States
 SE0, J, K, SE1 = 0, 1, 2, 3
 syms = {
-        (False, False): SE0,
-        (True, False): J,
-        (False, True): K,
-        (True, True): SE1,
+        (0, 0): SE0,
+        (1, 0): J,
+        (0, 1): K,
+        (1, 1): SE1,
 }
 
 def bitstr_to_num(bitstr):
@@ -110,7 +99,7 @@ def packet_decode(packet):
 
     return pid + ' ' + data
 
-class Decoder(sigrok.Decoder):
+class Decoder(srd.Decoder):
     id = 'usb'
     name = 'USB'
     desc = 'Universal Serial Bus'
@@ -122,19 +111,19 @@ class Decoder(sigrok.Decoder):
     inputs = ['logic']
     outputs = ['usb']
     # Probe names with a set of defaults
-    probes = {'dp':0, 'dm':1}
+    probes = [
+        {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
+        {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
+    ]
     options = {}
 
     def __init__(self):
-        self.probes = Decoder.probes.copy()
-        self.output_protocol = None
-        self.output_annotation = None
+        pass
 
     def start(self, metadata):
-        self.unitsize = metadata['unitsize']
         self.rate = metadata['samplerate']
-        # self.output_protocol = self.output_new(2)
-        self.output_annotation = self.output_new(1)
+        # self.out_proto = self.add(srd.SRD_OUTPUT_PROTO, 'usb')
+        self.out_ann = self.add(srd.SRD_OUTPUT_ANN, 'usb')
         if self.rate < 48000000:
             raise Exception("Sample rate not sufficient for USB decoding")
         # Initialise decoder state.
@@ -145,12 +134,12 @@ class Decoder(sigrok.Decoder):
     def decode(self, timeoffset, duration, data):
         out = []
 
-        for sample in sampleiter(data, self.unitsize):
+        # FIXME
+        for (samplenum, (dp, dm, x, y, z, a)) in data:
 
             self.scount += 1
 
-            sym = syms[sample.probe(self.probes['dp']),
-                       sample.probe(self.probes['dm'])]
+            sym = syms[dp, dm]
             if sym == self.sym:
                 continue
 
@@ -192,6 +181,6 @@ class Decoder(sigrok.Decoder):
             self.sym = sym
 
         if out != []:
-            # self.put(self.output_protocol, 0, 0, out_proto)
-            self.put(self.output_annotation, 0, 0, out)
+            # self.put(0, 0, self.out_proto, out_proto)
+            self.put(0, 0, self.out_ann, out)