decoders: Fix incorrect 'outputs' fields.

[libsigrokdecode.git] / decoders / spiflash / pd.py

diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py
index 536b55c56521f7e8bda7786115150d365810a988..5ee22740553efa2ca69ca1cef1f93a02d25006d1 100644 (file)
--- a/decoders/spiflash/pd.py
+++ b/decoders/spiflash/pd.py
@@ -78,7 +78,8 @@ class Decoder(srd.Decoder):
     desc = 'xx25 series SPI (NOR) flash chip protocol.'
     license = 'gplv2+'
     inputs = ['spi']
-    outputs = ['spiflash']
+    outputs = []
+    tags = ['IC', 'Memory']
     annotations = cmd_annotation_classes() + (
         ('bit', 'Bit'),
         ('field', 'Field'),
@@ -104,6 +105,7 @@ class Decoder(srd.Decoder):
         self.device_id = -1
         self.on_end_transaction = None
         self.end_current_transaction()
+        self.writestate = 0
 
         # Build dict mapping command keys to handler functions. Each
         # command in 'cmds' (defined in lists.py) has a matching
@@ -174,10 +176,11 @@ class Decoder(srd.Decoder):
 
     def handle_wren(self, mosi, miso):
         self.putx([Ann.WREN, self.cmd_ann_list()])
-        self.state = None
+        self.writestate = 1
 
     def handle_wrdi(self, mosi, miso):
-        pass # TODO
+        self.putx([Ann.WRDI, self.cmd_ann_list()])
+        self.writestate = 0
 
     def handle_rdid(self, mosi, miso):
         if self.cmdstate == 1:
@@ -215,6 +218,8 @@ class Decoder(srd.Decoder):
             self.putx([Ann.BIT, [decode_status_reg(miso)]])
             self.putx([Ann.FIELD, ['Status register']])
             self.putc([Ann.RDSR, self.cmd_ann_list()])
+            # Set write latch state.
+            self.writestate = 1 if (miso & (1 << 1)) else 0
         self.cmdstate += 1
 
     def handle_rdsr2(self, mosi, miso):
@@ -244,12 +249,14 @@ class Decoder(srd.Decoder):
             self.emit_cmd_byte()
         elif self.cmdstate == 2:
             # Byte 2: Master sends status register 1.
-            self.putx([Ann.BIT, [decode_status_reg(miso)]])
+            self.putx([Ann.BIT, [decode_status_reg(mosi)]])
             self.putx([Ann.FIELD, ['Status register 1']])
+            # Set write latch state.
+            self.writestate = 1 if (miso & (1 << 1)) else 0
         elif self.cmdstate == 3:
             # Byte 3: Master sends status register 2.
             # TODO: Decode status register 2 correctly.
-            self.putx([Ann.BIT, [decode_status_reg(miso)]])
+            self.putx([Ann.BIT, [decode_status_reg(mosi)]])
             self.putx([Ann.FIELD, ['Status register 2']])
             self.es_cmd = self.es
             self.putc([Ann.WRSR, self.cmd_ann_list()])
@@ -279,6 +286,8 @@ class Decoder(srd.Decoder):
         if self.cmdstate == 1:
             # Byte 1: Master sends command ID.
             self.emit_cmd_byte()
+            if self.writestate == 0:
+                self.putc([Ann.WARN, ['Warning: WREN might be missing']])
         elif self.cmdstate in (2, 3, 4):
             # Bytes 2/3/4: Master sends write address (24bits, MSB-first).
             self.emit_addr_bytes(mosi)
@@ -363,11 +372,12 @@ class Decoder(srd.Decoder):
         self.cmdstate += 1
 
     # TODO: Warn/abort if we don't see the necessary amount of bytes.
-    # TODO: Warn if WREN was not seen before.
     def handle_se(self, mosi, miso):
         if self.cmdstate == 1:
             # Byte 1: Master sends command ID.
             self.emit_cmd_byte()
+            if self.writestate == 0:
+                self.putx([Ann.WARN, ['Warning: WREN might be missing']])
         elif self.cmdstate in (2, 3, 4):
             # Bytes 2/3/4: Master sends sector address (24bits, MSB-first).
             self.emit_addr_bytes(mosi)
@@ -387,13 +397,15 @@ class Decoder(srd.Decoder):
     def handle_be(self, mosi, miso):
         pass # TODO
 
-    # TODO: Warn if WREN was not seen before.
     def handle_ce(self, mosi, miso):
         self.putx([Ann.CE, self.cmd_ann_list()])
+        if self.writestate == 0:
+            self.putx([Ann.WARN, ['Warning: WREN might be missing']])
 
-    # TODO: Warn if WREN was not seen before.
     def handle_ce2(self, mosi, miso):
         self.putx([Ann.CE2, self.cmd_ann_list()])
+        if self.writestate == 0:
+            self.putx([Ann.WARN, ['Warning: WREN might be missing']])
 
     def handle_pp(self, mosi, miso):
         # Page program: Master asserts CS#, sends PP command, sends 3-byte
@@ -462,8 +474,8 @@ class Decoder(srd.Decoder):
             self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]])
 
         if self.cmdstate == 6:
-            id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
-            self.device_id = id
+            id_ = self.ids[1] if self.manufacturer_id_first else self.ids[0]
+            self.device_id = id_
             self.es_cmd = self.es
             self.putc([Ann.REMS, self.cmd_vendor_dev_list()])
             self.state = None