decoders: Fix incorrect 'outputs' fields.

[libsigrokdecode.git] / decoders / spiflash / pd.py

diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py
index 3d525b9d775fed9412436740f0ca97d301237761..5ee22740553efa2ca69ca1cef1f93a02d25006d1 100644 (file)
--- a/decoders/spiflash/pd.py
+++ b/decoders/spiflash/pd.py
@@ -78,7 +78,8 @@ class Decoder(srd.Decoder):
     desc = 'xx25 series SPI (NOR) flash chip protocol.'
     license = 'gplv2+'
     inputs = ['spi']
-    outputs = ['spiflash']
+    outputs = []
+    tags = ['IC', 'Memory']
     annotations = cmd_annotation_classes() + (
         ('bit', 'Bit'),
         ('field', 'Field'),
@@ -217,6 +218,8 @@ class Decoder(srd.Decoder):
             self.putx([Ann.BIT, [decode_status_reg(miso)]])
             self.putx([Ann.FIELD, ['Status register']])
             self.putc([Ann.RDSR, self.cmd_ann_list()])
+            # Set write latch state.
+            self.writestate = 1 if (miso & (1 << 1)) else 0
         self.cmdstate += 1
 
     def handle_rdsr2(self, mosi, miso):
@@ -248,6 +251,8 @@ class Decoder(srd.Decoder):
             # Byte 2: Master sends status register 1.
             self.putx([Ann.BIT, [decode_status_reg(mosi)]])
             self.putx([Ann.FIELD, ['Status register 1']])
+            # Set write latch state.
+            self.writestate = 1 if (miso & (1 << 1)) else 0
         elif self.cmdstate == 3:
             # Byte 3: Master sends status register 2.
             # TODO: Decode status register 2 correctly.
@@ -469,8 +474,8 @@ class Decoder(srd.Decoder):
             self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]])
 
         if self.cmdstate == 6:
-            id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
-            self.device_id = id
+            id_ = self.ids[1] if self.manufacturer_id_first else self.ids[0]
+            self.device_id = id_
             self.es_cmd = self.es
             self.putc([Ann.REMS, self.cmd_vendor_dev_list()])
             self.state = None