srd: rename extra_probes to optional_probes in all PDs

[libsigrokdecode.git] / decoders / spi / spi.py

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index 07b8da2422dd048fa79a823072cb1f38384f3006..ff186ddcf56d6280101c671317ee8173a8cf404c 100644 (file)
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -37,6 +37,7 @@ CPHA_1 = 1 # Data is valid on the trailing clock edge
 MSB_FIRST = 0
 LSB_FIRST = 1
 
+# Key: (CPOL, CPHA). Value: SPI mode.
 spi_mode = {
     (0, 0): 0, # Mode 0
     (0, 1): 1, # Mode 1
@@ -48,6 +49,7 @@ spi_mode = {
 ANN_HEX = 0
 
 class Decoder(srd.Decoder):
+    api_version = 1
     id = 'spi'
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
@@ -57,13 +59,14 @@ class Decoder(srd.Decoder):
     inputs = ['logic']
     outputs = ['spi']
     probes = [
-        {'id': 'mosi', 'name': 'MOSI',
-         'desc': 'SPI MOSI line (Master out, slave in)'},
         {'id': 'miso', 'name': 'MISO',
          'desc': 'SPI MISO line (Master in, slave out)'},
+        {'id': 'mosi', 'name': 'MOSI',
+         'desc': 'SPI MOSI line (Master out, slave in)'},
         {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
         {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
     ]
+    optional_probes = [] # TODO
     options = {
         'cs_polarity': ['CS# polarity', ACTIVE_LOW],
         'cpol': ['Clock polarity', CPOL_0],
@@ -84,13 +87,6 @@ class Decoder(srd.Decoder):
         self.samplenum = -1
         self.cs_was_deasserted_during_data_word = 0
 
-        # Set protocol decoder option defaults.
-        self.cs_polarity = Decoder.options['cs_polarity'][1]
-        self.cpol = Decoder.options['cpol'][1]
-        self.cpha = Decoder.options['cpha'][1]
-        self.bitorder = Decoder.options['bitorder'][1]
-        self.wordsize = Decoder.options['wordsize'][1]
-
     def start(self, metadata):
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
         self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
@@ -99,11 +95,8 @@ class Decoder(srd.Decoder):
         return 'SPI: %d bytes received' % self.bytesreceived
 
     def decode(self, ss, es, data):
-        # HACK! At the moment the number of probes is not handled correctly.
-        # E.g. if an input file (-i foo.sr) has more than two probes enabled.
-        # for (samplenum, (mosi, sck, x, y, z, a)) in data:
-        # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
-        for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
+        # TODO: Either MISO or MOSI could be optional. CS# is optional.
+        for (samplenum, (miso, mosi, sck, cs)) in data:
 
             self.samplenum += 1 # FIXME
 
@@ -114,7 +107,7 @@ class Decoder(srd.Decoder):
             self.oldsck = sck
 
             # Sample data on rising/falling clock edge (depends on mode).
-            mode = spi_mode[self.cpol, self.cpha]
+            mode = spi_mode[self.options['cpol'], self.options['cpha']]
             if mode == 0 and sck == 0:   # Sample on rising clock edge
                     continue
             elif mode == 1 and sck == 1: # Sample on falling clock edge
@@ -127,26 +120,29 @@ class Decoder(srd.Decoder):
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
                 self.start_sample = samplenum
-                deasserted = cs if (self.cs_polarity == ACTIVE_LOW) else not c
+                active_low = (self.options['cs_polarity'] == ACTIVE_LOW)
+                deasserted = cs if active_low else not cs
                 if deasserted:
                     self.cs_was_deasserted_during_data_word = 1
 
+            ws = self.options['wordsize']
+
             # Receive MOSI bit into our shift register.
-            if self.bitorder == MSB_FIRST:
-                self.mosidata |= mosi << (self.wordsize - 1 - self.bitcount)
+            if self.options['bitorder'] == MSB_FIRST:
+                self.mosidata |= mosi << (ws - 1 - self.bitcount)
             else:
                 self.mosidata |= mosi << self.bitcount
 
             # Receive MISO bit into our shift register.
-            if self.bitorder == MSB_FIRST:
-                self.misodata |= miso << (self.wordsize - 1 - self.bitcount)
+            if self.options['bitorder'] == MSB_FIRST:
+                self.misodata |= miso << (ws - 1 - self.bitcount)
             else:
                 self.misodata |= miso << self.bitcount
 
             self.bitcount += 1
 
-            # Continue to receive if not a byte yet.
-            if self.bitcount != self.wordsize:
+            # Continue to receive if not enough bits were received, yet.
+            if self.bitcount != ws:
                 continue
 
             self.put(self.start_sample, self.samplenum, self.out_proto,