spi: Create the out_bitrate annotation unconditionally

[libsigrokdecode.git] / decoders / spi / pd.py

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index aec1fac4ec30e8614e3b0b9a405d3a8eafcf41bf..85bb1cb9e3195464fc55a983d3e87ecc78cf0baf 100644 (file)
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -70,9 +70,6 @@ spi_mode = {
     (1, 1): 3, # Mode 3
 }
 
-class SamplerateError(Exception):
-    pass
-
 class ChannelError(Exception):
     pass
 
@@ -124,6 +121,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.bitcount = 0
         self.misodata = self.mosidata = 0
@@ -137,10 +137,6 @@ class Decoder(srd.Decoder):
         self.cs_was_deasserted = False
         self.have_cs = self.have_miso = self.have_mosi = None
 
-    def metadata(self, key, value):
-        if key == srd.SRD_CONF_SAMPLERATE:
-            self.samplerate = value
-
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
@@ -149,6 +145,10 @@ class Decoder(srd.Decoder):
                 meta=(int, 'Bitrate', 'Bitrate during transfers'))
         self.bw = (self.options['wordsize'] + 7) // 8
 
+    def metadata(self, key, value):
+       if key == srd.SRD_CONF_SAMPLERATE:
+            self.samplerate = value
+
     def putw(self, data):
         self.put(self.ss_block, self.samplenum, self.out_ann, data)
 
@@ -209,17 +209,18 @@ class Decoder(srd.Decoder):
                 not self.cs_asserted(cs) if self.have_cs else False
 
         ws = self.options['wordsize']
+        bo = self.options['bitorder']
 
         # Receive MISO bit into our shift register.
         if self.have_miso:
-            if self.options['bitorder'] == 'msb-first':
+            if bo == 'msb-first':
                 self.misodata |= miso << (ws - 1 - self.bitcount)
             else:
                 self.misodata |= miso << self.bitcount
 
         # Receive MOSI bit into our shift register.
         if self.have_mosi:
-            if self.options['bitorder'] == 'msb-first':
+            if bo == 'msb-first':
                 self.mosidata |= mosi << (ws - 1 - self.bitcount)
             else:
                 self.mosidata |= mosi << self.bitcount
@@ -251,10 +252,11 @@ class Decoder(srd.Decoder):
         self.putdata()
 
         # Meta bitrate.
-        elapsed = 1 / float(self.samplerate)
-        elapsed *= (self.samplenum - self.ss_block + 1)
-        bitrate = int(1 / elapsed * self.options['wordsize'])
-        self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
+        if self.samplerate:
+            elapsed = 1 / float(self.samplerate)
+            elapsed *= (self.samplenum - self.ss_block + 1)
+            bitrate = int(1 / elapsed * ws)
+            self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
 
         if self.have_cs and self.cs_was_deasserted:
             self.putw([4, ['CS# was deasserted during this data word!']])
@@ -302,9 +304,6 @@ class Decoder(srd.Decoder):
         self.handle_bit(miso, mosi, clk, cs)
 
     def decode(self):
-        if not self.samplerate:
-            raise SamplerateError('Cannot decode without samplerate.')
-
         # The CLK input is mandatory. Other signals are (individually)
         # optional. Yet either MISO or MOSI (or both) must be provided.
         # Tell stacked decoders when we don't have a CS# signal.
@@ -330,12 +329,9 @@ class Decoder(srd.Decoder):
         # process the very first sample before checking for edges. The
         # previous implementation did this by seeding old values with
         # None, which led to an immediate "change" in comparison.
-        pins = self.wait({})
-        (clk, miso, mosi, cs) = pins
+        (clk, miso, mosi, cs) = self.wait({})
         self.find_clk_edge(miso, mosi, clk, cs, True)
 
         while True:
-            # Ignore identical samples early on (for performance reasons).
-            pins = self.wait(wait_cond)
-            (clk, miso, mosi, cs) = pins
+            (clk, miso, mosi, cs) = self.wait(wait_cond)
             self.find_clk_edge(miso, mosi, clk, cs, False)