spi: Fix warnings about CS# being de-asserted.

[libsigrokdecode.git] / decoders / spi / pd.py

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index cd40946c791ec5a1fb13edea8fbe6df75ed20e1f..78b167abb45d81082905d818fbcd464e761bb3fb 100644 (file)
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -109,7 +109,7 @@ class Decoder(srd.Decoder):
         self.mosibits = []
         self.startsample = -1
         self.samplenum = -1
-        self.cs_was_deasserted_during_data_word = 0
+        self.cs_was_deasserted = False
         self.oldcs = -1
         self.oldpins = None
         self.have_cs = self.have_miso = self.have_mosi = None
@@ -167,11 +167,12 @@ class Decoder(srd.Decoder):
         # If this is the first bit of a dataword, save its sample number.
         if self.bitcount == 0:
             self.startsample = self.samplenum
+            self.cs_was_deasserted = False
             if self.have_cs:
                 active_low = (self.options['cs_polarity'] == 'active-low')
-                deasserted = cs if active_low else not cs
+                deasserted = (cs == 1) if active_low else (cs == 0)
                 if deasserted:
-                    self.cs_was_deasserted_during_data_word = 1
+                    self.cs_was_deasserted = True
 
         ws = self.options['wordsize']
 
@@ -218,7 +219,7 @@ class Decoder(srd.Decoder):
         bitrate = int(1 / elapsed * self.options['wordsize'])
         self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
 
-        if self.have_cs and self.cs_was_deasserted_during_data_word:
+        if self.have_cs and self.cs_was_deasserted:
             self.putw([4, ['CS# was deasserted during this data word!']])
 
         self.reset_decoder_state()
@@ -266,6 +267,10 @@ class Decoder(srd.Decoder):
             self.have_mosi = (mosi in (0, 1))
             self.have_cs = (cs in (0, 1))
 
+            # Either MISO or MOSI (but not both) can be omitted.
+            if not (self.have_miso or self.have_mosi):
+                raise Exception('Either MISO or MOSI (or both) pins required.')
+
             # State machine.
             if self.state == 'IDLE':
                 self.find_clk_edge(miso, mosi, clk, cs)