self.samplerate = None
self.oldclk = 1
self.bitcount = 0
- self.mosidata = 0
- self.misodata = 0
- self.mosibits = []
+ self.misodata = self.mosidata = 0
self.misobits = []
+ self.mosibits = []
self.startsample = -1
self.samplenum = -1
- self.cs_was_deasserted_during_data_word = 0
+ self.cs_was_deasserted = False
self.oldcs = -1
self.oldpins = None
- self.have_cs = None
- self.have_miso = None
- self.have_mosi = None
+ self.have_cs = self.have_miso = self.have_mosi = None
self.state = 'IDLE'
def metadata(self, key, value):
def putw(self, data):
self.put(self.startsample, self.samplenum, self.out_ann, data)
- def putmisobit(self, i, data):
- self.put(self.misobits[i][1], self.misobits[i][2], self.out_ann, data)
+ def putdata(self):
+ # Pass MISO and MOSI bits and then data to the next PD up the stack.
+ so = self.misodata if self.have_miso else None
+ si = self.mosidata if self.have_mosi else None
+ so_bits = self.misobits if self.have_miso else None
+ si_bits = self.mosibits if self.have_mosi else None
+ self.putpw(['BITS', si_bits, so_bits])
+ self.putpw(['DATA', si, so])
+
+ # Bit annotations.
+ if self.have_miso:
+ for bit in self.misobits:
+ self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]])
+ if self.have_mosi:
+ for bit in self.mosibits:
+ self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]])
- def putmosibit(self, i, data):
- self.put(self.mosibits[i][1], self.mosibits[i][2], self.out_ann, data)
+ # Dataword annotations.
+ if self.have_miso:
+ ss, es = self.misobits[0][1], self.misobits[-1][2]
+ self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
+ if self.have_mosi:
+ ss, es = self.mosibits[0][1], self.mosibits[-1][2]
+ self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
+
+ def reset_decoder_state(self):
+ self.misodata = 0 if self.have_miso else None
+ self.mosidata = 0 if self.have_mosi else None
+ self.misobits = [] if self.have_miso else None
+ self.mosibits = [] if self.have_mosi else None
+ self.bitcount = 0
def handle_bit(self, miso, mosi, clk, cs):
# If this is the first bit of a dataword, save its sample number.
if self.bitcount == 0:
self.startsample = self.samplenum
+ self.cs_was_deasserted = False
if self.have_cs:
active_low = (self.options['cs_polarity'] == 'active-low')
- deasserted = cs if active_low else not cs
+ deasserted = (cs == 1) if active_low else (cs == 0)
if deasserted:
- self.cs_was_deasserted_during_data_word = 1
+ self.cs_was_deasserted = True
ws = self.options['wordsize']
+ # Receive MISO bit into our shift register.
+ if self.have_miso:
+ if self.options['bitorder'] == 'msb-first':
+ self.misodata |= miso << (ws - 1 - self.bitcount)
+ else:
+ self.misodata |= miso << self.bitcount
+
# Receive MOSI bit into our shift register.
if self.have_mosi:
if self.options['bitorder'] == 'msb-first':
else:
self.mosidata |= mosi << self.bitcount
- # Receive MISO bit into our shift register.
- if self.have_miso:
- if self.options['bitorder'] == 'msb-first':
- self.misodata |= miso << (ws - 1 - self.bitcount)
- else:
- self.misodata |= miso << self.bitcount
+ # Guesstimate the endsample for this bit (can be overridden below).
+ es = self.samplenum
+ if self.bitcount > 0:
+ es += self.samplenum - self.misobits[self.bitcount - 1][1]
if self.have_miso:
- self.misobits.append([miso, self.samplenum, -1])
+ self.misobits.append([miso, self.samplenum, es])
if self.have_mosi:
- self.mosibits.append([mosi, self.samplenum, -1])
- if self.bitcount != 0:
- if self.have_miso:
- self.misobits[self.bitcount - 1][2] = self.samplenum
- self.putmisobit(self.bitcount - 1, [3, ['%d' % miso]])
- if self.have_mosi:
- self.mosibits[self.bitcount - 1][2] = self.samplenum
- self.putmosibit(self.bitcount - 1, [2, ['%d' % mosi]])
+ self.mosibits.append([mosi, self.samplenum, es])
+
+ if self.bitcount > 0 and self.have_miso:
+ self.misobits[self.bitcount - 1][2] = self.samplenum
+ if self.bitcount > 0 and self.have_mosi:
+ self.mosibits[self.bitcount - 1][2] = self.samplenum
self.bitcount += 1
if self.bitcount != ws:
return
- si = self.mosidata if self.have_mosi else None
- so = self.misodata if self.have_miso else None
- si_bits = self.mosibits if self.have_mosi else None
- so_bits = self.misobits if self.have_miso else None
-
- # Pass MOSI and MISO to the next PD up the stack.
- self.putpw(['DATA', si, so])
- self.putpw(['BITS', si_bits, so_bits])
-
- # Annotations.
- if self.have_miso:
- self.putw([0, ['%02X' % self.misodata]])
- if self.have_mosi:
- self.putw([1, ['%02X' % self.mosidata]])
+ self.putdata()
# Meta bitrate.
- elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
+ elapsed = 1 / float(self.samplerate)
+ elapsed *= (self.samplenum - self.startsample + 1)
bitrate = int(1 / elapsed * self.options['wordsize'])
self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
- if self.have_cs and self.cs_was_deasserted_during_data_word:
+ if self.have_cs and self.cs_was_deasserted:
self.putw([4, ['CS# was deasserted during this data word!']])
- # Reset decoder state.
- self.misodata = 0 if self.have_miso else None
- self.mosidata = 0 if self.have_mosi else None
- self.misobits = [] if self.have_miso else None
- self.mosibits = [] if self.have_mosi else None
- self.bitcount = 0
+ self.reset_decoder_state()
def find_clk_edge(self, miso, mosi, clk, cs):
if self.have_cs and self.oldcs != cs:
['CS-CHANGE', self.oldcs, cs])
self.oldcs = cs
# Reset decoder state when CS# changes (and the CS# pin is used).
- self.misodata = 0 if self.have_miso else None
- self.mosidata = 0 if self.have_mosi else None
- self.bitcount = 0
+ self.reset_decoder_state()
# Ignore sample if the clock pin hasn't changed.
if clk == self.oldclk:
self.have_mosi = (mosi in (0, 1))
self.have_cs = (cs in (0, 1))
+ # Either MISO or MOSI (but not both) can be omitted.
+ if not (self.have_miso or self.have_mosi):
+ raise Exception('Either MISO or MOSI (or both) pins required.')
+
# State machine.
if self.state == 'IDLE':
self.find_clk_edge(miso, mosi, clk, cs)
projects / libsigrokdecode.git / blobdiff