## This file is part of the sigrok project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
import sigrokdecode as srd
+# Chip-select options
+ACTIVE_LOW = 0
+ACTIVE_HIGH = 1
+
+# Clock polarity options
+CPOL_0 = 0 # Clock is low when inactive
+CPOL_1 = 1 # Clock is high when inactive
+
+# Clock phase options
+CPHA_0 = 0 # Data is valid on the rising clock edge
+CPHA_1 = 1 # Data is valid on the falling clock edge
+
+# Bit order options
+MSB_FIRST = 0
+LSB_FIRST = 1
+
+spi_mode = {
+ (0, 0): 0, # Mode 0
+ (0, 1): 1, # Mode 1
+ (1, 0): 2, # Mode 2
+ (1, 1): 3, # Mode 3
+}
+
+# Annotation formats
+ANN_HEX = 0
+
class Decoder(srd.Decoder):
id = 'spi'
name = 'SPI'
inputs = ['logic']
outputs = ['spi']
probes = [
- {'id': 'sdata', 'name': 'DATA', 'desc': 'SPI data line (MISO or MOSI)'},
+ {'id': 'mosi', 'name': 'MOSI',
+ 'desc': 'SPI MOSI line (Master out, slave in)'},
+ {'id': 'miso', 'name': 'MISO',
+ 'desc': 'SPI MISO line (Master in, slave out)'},
{'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
+ {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
+ ]
+ options = {
+ 'cs_active_low': ['CS# active low', ACTIVE_LOW],
+ 'cpol': ['Clock polarity', CPOL_0],
+ 'cpha': ['Clock phase', CPHA_0],
+ 'bitorder': ['Bit order within the SPI data', MSB_FIRST],
+ 'wordsize': ['Word size of SPI data', 8], # 1-64?
+ }
+ annotations = [
+ ['Hex', 'SPI data bytes in hex format'],
]
- options = {}
- annotations = []
def __init__(self):
self.oldsck = 1
- self.rxcount = 0
- self.rxdata = 0
+ self.bitcount = 0
+ self.mosidata = 0
+ self.misodata = 0
self.bytesreceived = 0
+ self.samplenum = -1
+
+ # Set protocol decoder option defaults.
+ self.cs_active_low = Decoder.options['cs_active_low'][1]
+ self.cpol = Decoder.options['cpol'][1]
+ self.cpha = Decoder.options['cpha'][1]
+ self.bitorder = Decoder.options['bitorder'][1]
+ self.wordsize = Decoder.options['wordsize'][1]
def start(self, metadata):
- # self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
+ self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
def report(self):
def decode(self, ss, es, data):
# HACK! At the moment the number of probes is not handled correctly.
# E.g. if an input file (-i foo.sr) has more than two probes enabled.
- for (samplenum, (sdata, sck, x, y, z, a)) in data:
+ # for (samplenum, (mosi, sck, x, y, z, a)) in data:
+ # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
+ for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
- # Sample SDATA on rising SCK
+ self.samplenum += 1 # FIXME
+
+ # Ignore sample if the clock pin hasn't changed.
if sck == self.oldsck:
continue
+
self.oldsck = sck
- if not sck:
- continue
- # If this is first bit, save timestamp
- if self.rxcount == 0:
- self.time = ss # FIXME
- # Receive bit into our shift register
- if sdata:
- self.rxdata |= 1 << (7 - self.rxcount)
- self.rxcount += 1
- # Continue to receive if not a byte yet
- if self.rxcount != 8:
+ # Sample data on rising/falling clock edge (depends on mode).
+ mode = spi_mode[self.cpol, self.cpha]
+ if mode == 0 and sck == 0: # Sample on rising clock edge
+ continue
+ elif mode == 1 and sck == 1: # Sample on falling clock edge
+ continue
+ elif mode == 2 and sck == 1: # Sample on falling clock edge
+ continue
+ elif mode == 3 and sck == 0: # Sample on rising clock edge
+ continue
+
+ # If this is the first bit, save its sample number.
+ if self.bitcount == 0:
+ self.start_sample = samplenum
+
+ # Receive MOSI bit into our shift register.
+ if self.bitorder == MSB_FIRST:
+ self.mosidata |= mosi << (self.wordsize - 1 - self.bitcount)
+ else:
+ self.mosidata |= mosi << self.bitcount
+
+ # Receive MISO bit into our shift register.
+ if self.bitorder == MSB_FIRST:
+ self.misodata |= miso << (self.wordsize - 1 - self.bitcount)
+ else:
+ self.misodata |= miso << self.bitcount
+
+ self.bitcount += 1
+
+ # Continue to receive if not a byte yet.
+ if self.bitcount != self.wordsize:
continue
- # Received a byte, pass up to sigrok
- outdata = {'time':self.time, # FIXME
- 'duration':ss + es - self.time, # FIXME
- 'data':self.rxdata,
- 'display':('%02X' % self.rxdata),
- 'type':'spi',
- }
- # self.put(0, 0, self.out_proto, out_proto)
- self.put(0, 0, self.out_ann, outdata)
- # Reset decoder state
- self.rxdata = 0
- self.rxcount = 0
- # Keep stats for summary
+
+ self.put(self.start_sample, self.samplenum, self.out_proto,
+ ['data', self.mosidata, self.misodata])
+ self.put(self.start_sample, self.samplenum, self.out_ann,
+ [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
+ self.misodata)]])
+
+ # Reset decoder state.
+ self.mosidata = 0
+ self.misodata = 0
+ self.bitcount = 0
+
+ # Keep stats for summary.
self.bytesreceived += 1
projects / libsigrokdecode.git / blobdiff