srd: SPI: Support sampling on rising/falling CLK edge.

[libsigrokdecode.git] / decoders / spi.py

diff --git a/decoders/spi.py b/decoders/spi.py
index 44d07c260f64bf19d057dc2fac42533d42e91d2d..480174ee60ba8befe6ebdf1d9ab676240dfb0085 100644 (file)
--- a/decoders/spi.py
+++ b/decoders/spi.py
@@ -21,6 +21,29 @@
 
 import sigrokdecode as srd
 
+# Chip-select options
+ACTIVE_LOW = 0
+ACTIVE_HIGH = 1
+
+# Clock polarity options
+CPOL_0 = 0 # Clock is low when inactive
+CPOL_1 = 1 # Clock is high when inactive
+
+# Clock phase options
+CPHA_0 = 0 # Data is valid on the rising clock edge
+CPHA_1 = 1 # Data is valid on the falling clock edge
+
+# Bit order options
+MSB_FIRST = 0
+LSB_FIRST = 1
+
+spi_mode = {
+    (0, 0): 0, # Mode 0
+    (0, 1): 1, # Mode 1
+    (1, 0): 2, # Mode 2
+    (1, 1): 3, # Mode 3
+}
+
 # Annotation formats
 ANN_HEX = 0
 
@@ -43,7 +66,13 @@ class Decoder(srd.Decoder):
         {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
         {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
     ]
-    options = {}
+    options = {
+        'cs_active_low': ['CS# active low', ACTIVE_LOW],
+        'cpol': ['Clock polarity', CPOL_0],
+        'cpha': ['Clock phase', CPHA_0],
+        'bitorder': ['Bit order within the SPI data', MSB_FIRST],
+        'wordsize': ['Word size of SPI data', 8], # 1-64?
+    }
     annotations = [
         ['Hex', 'SPI data bytes in hex format'],
     ]
@@ -56,6 +85,13 @@ class Decoder(srd.Decoder):
         self.bytesreceived = 0
         self.samplenum = -1
 
+        # Set protocol decoder option defaults.
+        self.cs_active_low = Decoder.options['cs_active_low'][1]
+        self.cpol = Decoder.options['cpol'][1]
+        self.cpha = Decoder.options['cpha'][1]
+        self.bitorder = Decoder.options['bitorder'][1]
+        self.wordsize = Decoder.options['wordsize'][1]
+
     def start(self, metadata):
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
         self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
@@ -72,27 +108,43 @@ class Decoder(srd.Decoder):
 
             self.samplenum += 1 # FIXME
 
-            # Sample data on rising SCK edges.
+            # Ignore sample if the clock pin hasn't changed.
             if sck == self.oldsck:
                 continue
+
             self.oldsck = sck
-            if sck == 0:
-                continue
+
+            # Sample data on rising/falling clock edge (depends on mode).
+            mode = spi_mode[self.cpol, self.cpha]
+            if mode == 0 and sck == 0:   # Sample on rising clock edge
+                    continue
+            elif mode == 1 and sck == 1: # Sample on falling clock edge
+                    continue
+            elif mode == 2 and sck == 1: # Sample on falling clock edge
+                    continue
+            elif mode == 3 and sck == 0: # Sample on rising clock edge
+                    continue
 
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
                 self.start_sample = samplenum
 
-            # Receive bit into our shift register.
-            if mosi == 1:
-                self.mosidata |= 1 << (7 - self.bitcount)
-            if miso == 1:
-                self.misodata |= 1 << (7 - self.bitcount)
+            # Receive MOSI bit into our shift register.
+            if self.bitorder == MSB_FIRST:
+                self.mosidata |= mosi << (self.wordsize - 1 - self.bitcount)
+            else:
+                self.mosidata |= mosi << self.bitcount
+
+            # Receive MISO bit into our shift register.
+            if self.bitorder == MSB_FIRST:
+                self.misodata |= miso << (self.wordsize - 1 - self.bitcount)
+            else:
+                self.misodata |= miso << self.bitcount
 
             self.bitcount += 1
 
             # Continue to receive if not a byte yet.
-            if self.bitcount != 8:
+            if self.bitcount != self.wordsize:
                 continue
 
             self.put(self.start_sample, self.samplenum, self.out_proto,