##
## This file is part of the libsigrokdecode project.
##
-## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
import sigrokdecode as srd
+from common.srdhelper import bcd2int
-# Return the specified BCD number (max. 8 bits) as integer.
-def bcd2int(b):
- return (b & 0x0f) + ((b >> 4) * 10)
+def reg_list():
+ l = []
+ for i in range(8 + 1):
+ l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i))
+
+ return tuple(l)
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 3
id = 'rtc8564'
name = 'RTC-8564'
longname = 'Epson RTC-8564 JE/NB'
desc = 'Realtime clock module protocol.'
license = 'gplv2+'
inputs = ['i2c']
- outputs = ['rtc8564']
- probes = []
- optional_probes = [
- {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
- {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
- {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
- ]
- options = {}
- annotations = [
- ['text', 'Human-readable text'],
- ]
-
- def __init__(self, **kwargs):
+ outputs = []
+ tags = ['Clock/timing']
+ annotations = reg_list() + (
+ ('read', 'Read date/time'),
+ ('write', 'Write date/time'),
+ ('bit-reserved', 'Reserved bit'),
+ ('bit-vl', 'VL bit'),
+ ('bit-century', 'Century bit'),
+ ('reg-read', 'Register read'),
+ ('reg-write', 'Register write'),
+ )
+ annotation_rows = (
+ ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
+ ('regs', 'Register access', (14, 15)),
+ ('date-time', 'Date/time', (9, 10)),
+ )
+
+ def __init__(self):
+ self.reset()
+
+ def reset(self):
self.state = 'IDLE'
self.hours = -1
self.minutes = -1
self.seconds = -1
self.days = -1
+ self.weekdays = -1
self.months = -1
self.years = -1
+ self.bits = []
def start(self):
- # self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
def putx(self, data):
self.put(self.ss, self.es, self.out_ann, data)
+ def putd(self, bit1, bit2, data):
+ self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
+
+ def putr(self, bit):
+ self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
+ [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
+
def handle_reg_0x00(self, b): # Control register 1
pass
ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
'event occurs\n' % (tie, s)
- self.putx([0, [ann]])
+ self.putx([1, [ann]])
- def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
- self.seconds = bcd2int(b & 0x7f)
- self.putx([0, ['Seconds: %d' % self.seconds]])
+ def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
vl = 1 if (b & (1 << 7)) else 0
- self.putx([0, ['Voltage low (VL) bit: %d' % vl]])
+ self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
+ 'VL: %d' % vl, 'VL']])
+ s = self.seconds = bcd2int(b & 0x7f)
+ self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
def handle_reg_0x03(self, b): # Minutes
- self.minutes = bcd2int(b & 0x7f)
- self.putx([0, ['Minutes: %d' % self.minutes]])
+ self.putr(7)
+ m = self.minutes = bcd2int(b & 0x7f)
+ self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
def handle_reg_0x04(self, b): # Hours
- self.hours = bcd2int(b & 0x3f)
- self.putx([0, ['Hours: %d' % self.hours]])
+ self.putr(7)
+ self.putr(6)
+ h = self.hours = bcd2int(b & 0x3f)
+ self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])
def handle_reg_0x05(self, b): # Days
- self.days = bcd2int(b & 0x3f)
- self.putx([0, ['Days: %d' % self.days]])
-
- def handle_reg_0x06(self, b): # Day counter
- pass
-
- def handle_reg_0x07(self, b): # Months / century
- # TODO: Handle century bit.
- self.months = bcd2int(b & 0x1f)
- self.putx([0, ['Months: %d' % self.months]])
+ self.putr(7)
+ self.putr(6)
+ d = self.days = bcd2int(b & 0x3f)
+ self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])
+
+ def handle_reg_0x06(self, b): # Weekdays
+ for i in (7, 6, 5, 4, 3):
+ self.putr(i)
+ w = self.weekdays = bcd2int(b & 0x07)
+ self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])
+
+ def handle_reg_0x07(self, b): # Months / century bit
+ c = 1 if (b & (1 << 7)) else 0
+ self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
+ 'Cent: %d' % c, 'C: %d' % c, 'C']])
+ self.putr(6)
+ self.putr(5)
+ m = self.months = bcd2int(b & 0x1f)
+ self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
def handle_reg_0x08(self, b): # Years
- self.years = bcd2int(b & 0xff)
- self.putx([0, ['Years: %d' % self.years]])
+ y = self.years = bcd2int(b & 0xff)
+ self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
def handle_reg_0x09(self, b): # Alarm, minute
pass
def decode(self, ss, es, data):
cmd, databyte = data
+ # Collect the 'BITS' packet, then return. The next packet is
+ # guaranteed to belong to these bits we just stored.
+ if cmd == 'BITS':
+ self.bits = databyte
+ return
+
# Store the start/end samples of this I²C packet.
self.ss, self.es = ss, es
if cmd != 'START':
return
self.state = 'GET SLAVE ADDR'
- self.block_start_sample = ss
+ self.ss_block = ss
elif self.state == 'GET SLAVE ADDR':
# Wait for an address write operation.
# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
return
# Otherwise: Get data bytes until a STOP condition occurs.
if cmd == 'DATA WRITE':
+ r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
+ self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
+ 'WR %s' % s, 'WR', 'W']])
handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
handle_reg(databyte)
self.reg += 1
# TODO: Handle read/write of only parts of these items.
d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
self.years, self.hours, self.minutes, self.seconds)
- self.put(self.block_start_sample, es, self.out_ann,
- [0, ['Written date/time: %s' % d]])
+ self.put(self.ss_block, es, self.out_ann,
+ [9, ['Write date/time: %s' % d, 'Write: %s' % d,
+ 'W: %s' % d]])
self.state = 'IDLE'
else:
pass # TODO
pass # TODO
elif self.state == 'READ RTC REGS2':
if cmd == 'DATA READ':
+ r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
+ self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
+ 'RR %s' % s, 'RR', 'R']])
handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
handle_reg(databyte)
self.reg += 1
elif cmd == 'STOP':
d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
self.years, self.hours, self.minutes, self.seconds)
- self.put(self.block_start_sample, es, self.out_ann,
- [0, ['Read date/time: %s' % d]])
+ self.put(self.ss_block, es, self.out_ann,
+ [10, ['Read date/time: %s' % d, 'Read: %s' % d,
+ 'R: %s' % d]])
self.state = 'IDLE'
else:
pass # TODO?
- else:
- raise Exception('Invalid state: %s' % self.state)
-
projects / libsigrokdecode.git / blobdiff