## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2014 Torsten Duwe <duwe@suse.de>
+## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
import sigrokdecode as srd
+class SamplerateError(Exception):
+ pass
+
class Decoder(srd.Decoder):
- api_version = 2
+ api_version = 3
id = 'pwm'
name = 'PWM'
longname = 'Pulse-width modulation'
desc = 'Analog level encoded in duty cycle percentage.'
license = 'gplv2+'
inputs = ['logic']
- outputs = ['pwm']
+ outputs = []
+ tags = ['Encoding']
channels = (
- {'id': 'pwm', 'name': 'PWM in', 'desc': 'Modulation pulses'},
+ {'id': 'data', 'name': 'Data', 'desc': 'Data line'},
)
options = (
- {'id': 'new_cycle_edge', 'desc': 'New cycle on which edge',
- 'default': 'rising', 'values': ('rising', 'falling')},
+ {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-high',
+ 'values': ('active-low', 'active-high')},
)
annotations = (
- ('value', 'PWM value'),
+ ('duty-cycle', 'Duty cycle'),
+ ('period', 'Period'),
+ )
+ annotation_rows = (
+ ('duty-cycle', 'Duty cycle', (0,)),
+ ('period', 'Period', (1,)),
)
binary = (
('raw', 'RAW file'),
)
- def __init__(self, **kwargs):
- self.ss = self.es = -1
- self.high = 1
- self.low = 1
- self.lastedge = 0
- self.oldpin = 0
- self.startedge = 0
- self.num_cycles = 0
+ def __init__(self):
+ self.reset()
+
+ def reset(self):
+ self.samplerate = None
+ self.ss_block = self.es_block = None
+
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
def start(self):
- self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
- self.out_bin = self.register(srd.OUTPUT_BINARY)
- self.out_freq = self.register(srd.OUTPUT_META,
- meta=(int, 'Frequency', 'PWM base (cycle) frequency'))
- self.startedge = 0
- if self.options['new_cycle_edge'] == 'falling':
- self.startedge = 1
+ self.out_binary = self.register(srd.OUTPUT_BINARY)
+ self.out_average = \
+ self.register(srd.OUTPUT_META,
+ meta=(float, 'Average', 'PWM base (cycle) frequency'))
def putx(self, data):
- self.put(self.ss, self.es, self.out_ann, data)
+ self.put(self.ss_block, self.es_block, self.out_ann, data)
- def putp(self, data):
- self.put(self.ss, self.es, self.out_python, data)
+ def putp(self, period_t):
+ # Adjust granularity.
+ if period_t == 0 or period_t >= 1:
+ period_s = '%.1f s' % (period_t)
+ elif period_t <= 1e-12:
+ period_s = '%.1f fs' % (period_t * 1e15)
+ elif period_t <= 1e-9:
+ period_s = '%.1f ps' % (period_t * 1e12)
+ elif period_t <= 1e-6:
+ period_s = '%.1f ns' % (period_t * 1e9)
+ elif period_t <= 1e-3:
+ period_s = '%.1f μs' % (period_t * 1e6)
+ else:
+ period_s = '%.1f ms' % (period_t * 1e3)
+
+ self.put(self.ss_block, self.es_block, self.out_ann, [1, [period_s]])
def putb(self, data):
- self.put(self.num_cycles, self.num_cycles, self.out_bin, data)
-
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
- # Ignore identical samples early on (for performance reasons).
- if self.oldpin == pins[0]:
- continue
-
- if self.oldpin == 0: # Rising edge.
- self.low = self.samplenum - self.lastedge
- else:
- self.high = self.samplenum - self.lastedge
-
- if self.oldpin == self.startedge:
- self.es = self.samplenum # This interval ends at this edge.
- if self.ss >= 0: # Have we completed a hi-lo sequence?
- self.putx([0, ["%d%%" % ((100 * self.high) // (self.high + self.low))]])
- self.putb((0, bytes([(256 * self.high) // (self.high + self.low)])))
- self.num_cycles += 1
- else:
- # Mid-interval.
- # This interval started at the previous edge.
- self.ss = self.lastedge
-
- self.lastedge = self.samplenum
- self.oldpin = pins[0]
+ self.put(self.ss_block, self.es_block, self.out_binary, data)
+
+ def decode(self):
+ if not self.samplerate:
+ raise SamplerateError('Cannot decode without samplerate.')
+
+ num_cycles = 0
+ average = 0
+
+ # Wait for an "active" edge (depends on config). This starts
+ # the first full period of the inspected signal waveform.
+ self.wait({0: 'f' if self.options['polarity'] == 'active-low' else 'r'})
+ self.first_samplenum = self.samplenum
+
+ # Keep getting samples for the period's middle and terminal edges.
+ # At the same time that last sample starts the next period.
+ while True:
+
+ # Get the next two edges. Setup some variables that get
+ # referenced in the calculation and in put() routines.
+ start_samplenum = self.samplenum
+ self.wait({0: 'e'})
+ end_samplenum = self.samplenum
+ self.wait({0: 'e'})
+ self.ss_block = start_samplenum
+ self.es_block = self.samplenum
+
+ # Calculate the period, the duty cycle, and its ratio.
+ period = self.samplenum - start_samplenum
+ duty = end_samplenum - start_samplenum
+ ratio = float(duty / period)
+
+ # Report the duty cycle in percent.
+ percent = float(ratio * 100)
+ self.putx([0, ['%f%%' % percent]])
+
+ # Report the duty cycle in the binary output.
+ self.putb([0, bytes([int(ratio * 256)])])
+
+ # Report the period in units of time.
+ period_t = float(period / self.samplerate)
+ self.putp(period_t)
+
+ # Update and report the new duty cycle average.
+ num_cycles += 1
+ average += percent
+ self.put(self.first_samplenum, self.es_block, self.out_average,
+ float(average / num_cycles))
projects / libsigrokdecode.git / blobdiff