##
## This file is part of the libsigrokdecode project.
##
-## Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2013-2016 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
-# Parallel (sync) bus protocol decoder
-
import sigrokdecode as srd
'''
-Protocol output format:
+OUTPUT_PYTHON format:
Packet:
[<ptype>, <pdata>]
word <worditemcount> is 7, and so on.
'''
-def probe_list(num_probes):
- l = []
- for i in range(num_probes):
+def channel_list(num_channels):
+ l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
+ for i in range(num_channels):
d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
l.append(d)
- return l
+ return tuple(l)
+
+class ChannelError(Exception):
+ pass
+
+NUM_CHANNELS = 8
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 3
id = 'parallel'
name = 'Parallel'
longname = 'Parallel sync bus'
license = 'gplv2+'
inputs = ['logic']
outputs = ['parallel']
- probes = [
- {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'},
- ]
- optional_probes = probe_list(8)
- options = {
- 'clock_edge': ['Clock edge to sample on', 'rising'],
- 'wordsize': ['Word size of the data', 1],
- 'endianness': ['Endianness of the data', 'little'],
- 'format': ['Data format', 'hex'],
- }
- annotations = [
- ['items', 'Items'],
- ['words', 'Words'],
- ]
+ optional_channels = channel_list(NUM_CHANNELS)
+ options = (
+ {'id': 'clock_edge', 'desc': 'Clock edge to sample on',
+ 'default': 'rising', 'values': ('rising', 'falling')},
+ {'id': 'wordsize', 'desc': 'Data wordsize', 'default': 1},
+ {'id': 'endianness', 'desc': 'Data endianness',
+ 'default': 'little', 'values': ('little', 'big')},
+ )
+ annotations = (
+ ('items', 'Items'),
+ ('words', 'Words'),
+ )
def __init__(self):
- self.oldclk = None
self.items = []
self.itemcount = 0
self.saved_item = None
- self.samplenum = 0
- self.oldpins = None
self.ss_item = self.es_item = None
self.first = True
- self.state = 'IDLE'
+ self.num_channels = 0
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'parallel')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'parallel')
+ def start(self):
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
- def report(self):
- pass
+ # Assume that the initial pin state of all pins is logic 1.
+ self.initial_pins = [1] * (NUM_CHANNELS + 1)
def putpb(self, data):
- self.put(self.ss_item, self.es_item, self.out_proto, data)
+ self.put(self.ss_item, self.es_item, self.out_python, data)
def putb(self, data):
self.put(self.ss_item, self.es_item, self.out_ann, data)
def putpw(self, data):
- self.put(self.ss_word, self.es_word, self.out_proto, data)
+ self.put(self.ss_word, self.es_word, self.out_python, data)
def putw(self, data):
self.put(self.ss_word, self.es_word, self.out_ann, data)
self.ss_word = self.samplenum
# Get the bits for this item.
- item, used_pins = 0, datapins.count(b'\x01') + datapins.count(b'\x00')
+ item, used_pins = 0, datapins.count(1) + datapins.count(0)
for i in range(used_pins):
item |= datapins[i] << i
self.items.append(item)
self.itemcount += 1
- if self.first == True:
+ if self.first:
# Save the start sample and item for later (no output yet).
self.ss_item = self.samplenum
self.first = False
if self.itemcount < ws:
return
- # Output annotations/proto for a word (a collection of items).
+ # Output annotations/python for a word (a collection of items).
word = 0
for i in range(ws):
if endian == 'little':
self.itemcount, self.items = 0, []
- def find_clk_edge(self, clk, datapins):
- # Ignore sample if the clock pin hasn't changed.
- if clk == self.oldclk:
- return
- self.oldclk = clk
-
- # Sample data on rising/falling clock edge (depends on config).
- c = self.options['clock_edge']
- if c == 'rising' and clk == 0: # Sample on rising clock edge.
- return
- elif c == 'falling' and clk == 1: # Sample on falling clock edge.
- return
-
- # Found the correct clock edge, now get the bits.
- self.handle_bits(datapins)
-
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
-
- # Ignore identical samples early on (for performance reasons).
- if self.oldpins == pins:
- continue
- self.oldpins = pins
-
- # State machine.
- if self.state == 'IDLE':
- self.find_clk_edge(pins[0], pins[1:])
- else:
- raise Exception('Invalid state: %s' % self.state)
-
+ def decode(self):
+ for i in range(len(self.optional_channels)):
+ if self.has_channel(i):
+ self.num_channels += 1
+
+ if self.num_channels == 0:
+ raise ChannelError('At least one channel has to be supplied.')
+
+ if not self.has_channel(0):
+ # CLK was not supplied, sample on ANY edge of ANY of the pins
+ # (but only of those pins that were actually supplied).
+ conds = []
+ for i in range(1, len(self.optional_channels)):
+ if self.has_channel(i):
+ conds.append({i: 'e'})
+ while True:
+ self.handle_bits(self.wait(conds[:])[1:])
+ else:
+ # Sample on the rising or falling CLK edge (depends on config).
+ while True:
+ pins = self.wait({0: self.options['clock_edge'][0]})
+ self.handle_bits(pins[1:])
projects / libsigrokdecode.git / blobdiff