import sigrokdecode as srd
# Annotation feed formats
-ANN_ASCII = 0
-ANN_DEC = 1
-ANN_HEX = 2
-ANN_OCT = 3
-ANN_BITS = 4
+ANN_LINK = 0
+ANN_NETWORK = 1
+ANN_TRANSFER = 2
class Decoder(srd.Decoder):
api_version = 1
'overdrive': ['Overdrive', 0],
}
annotations = [
- ['ASCII', 'Data bytes as ASCII characters'],
- ['Decimal', 'Databytes as decimal, integer values'],
- ['Hex', 'Data bytes in hex format'],
- ['Octal', 'Data bytes as octal numbers'],
- ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
+ ['Link', 'Link layer events (reset, presence, bit slots)'],
+ ['Network', 'Network layer events (device addressing)'],
+ ['Transfer', 'Transfer layer events'],
]
- def putx(self, data):
- self.put(self.startsample, self.samplenum - 1, self.out_ann, data)
-
def __init__(self, **kwargs):
# Common variables
self.samplenum = 0
# Link layer variables
- self.lnk_state = 'WAIT FOR EVENT'
- self.lnk_event = 'NONE'
- self.lnk_start = -1
- self.lnk_bit = -1
- self.lnk_cnt = 0
- self.lnk_byte = -1
+ self.lnk_state = 'WAIT FOR FALLING EDGE'
+ self.lnk_event = 'NONE'
+ self.lnk_fall = 0
+ self.lnk_present = 0
+ self.lnk_bit = 0
# Network layer variables
- self.net_state = 'WAIT FOR EVENT'
- self.net_event = 'NONE'
- self.net_command = -1
+ self.net_state = 'IDLE'
+ self.net_cnt = 0
+ self.net_search = "P"
+ self.net_data_p = 0x0
+ self.net_data_n = 0x0
+ self.net_data = 0x0
+ self.net_rom = 0x0000000000000000
# Transport layer variables
- self.trn_state = 'WAIT FOR EVENT'
- self.trn_event = 'NONE'
-
- self.data_sample = -1
- self.cur_data_bit = 0
- self.databyte = 0
- self.startsample = -1
+ self.trn_state = 'IDLE'
def start(self, metadata):
self.samplerate = metadata['samplerate']
self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'onewire')
+ self.out_ann = self.add(srd.OUTPUT_ANN , 'onewire')
# The width of the 1-Wire time base (30us) in number of samples.
# TODO: optimize this value
- self.time_base = float(self.samplerate) / float(0.000030)
+ self.time_base = float(self.samplerate) * float(0.000030)
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_LINK, ['time_base = %d' % self.time_base]])
def report(self):
pass
- def get_data_sample(self, owr):
- # Skip samples until we're in the middle of the start bit.
- if not self.reached_data_sample():
- return
-
- self.data_sample = owr
-
- self.cur_data_bit = 0
- self.databyte = 0
- self.startsample = -1
-
- self.state = 'GET DATA BITS'
-
- self.put(self.cycle_start, self.samplenum, self.out_proto,
- ['STARTBIT', self.startbit])
- self.put(self.cycle_start, self.samplenum, self.out_ann,
- [ANN_ASCII, ['Start bit', 'Start', 'S']])
-
- def get_data_bits(self, owr):
- # Skip samples until we're in the middle of the desired data bit.
- if not self.reached_bit(self.cur_data_bit + 1):
- return
-
- # Save the sample number where the data byte starts.
- if self.startsample == -1:
- self.startsample = self.samplenum
-
- # Get the next data bit in LSB-first or MSB-first fashion.
- if self.options['bit_order'] == 'lsb-first':
- self.databyte >>= 1
- self.databyte |= \
- (owr << (self.options['num_data_bits'] - 1))
- elif self.options['bit_order'] == 'msb-first':
- self.databyte <<= 1
- self.databyte |= (owr << 0)
- else:
- raise Exception('Invalid bit order value: %s',
- self.options['bit_order'])
-
- # Return here, unless we already received all data bits.
- # TODO? Off-by-one?
- if self.cur_data_bit < self.options['num_data_bits'] - 1:
- self.cur_data_bit += 1
- return
-
- self.state = 'GET PARITY BIT'
-
- self.put(self.startsample, self.samplenum - 1, self.out_proto,
- ['DATA', self.databyte])
-
- self.putx([ANN_ASCII, [chr(self.databyte)]])
- self.putx([ANN_DEC, [str(self.databyte)]])
- self.putx([ANN_HEX, [hex(self.databyte),
- hex(self.databyte)[2:]]])
- self.putx([ANN_OCT, [oct(self.databyte),
- oct(self.databyte)[2:]]])
- self.putx([ANN_BITS, [bin(self.databyte),
- bin(self.databyte)[2:]]])
-
def decode(self, ss, es, data):
- for (self.samplenum, owr) in data:
-
- # First sample: Save OWR value.
- if self.oldbit == None:
- self.oldbit = owr
- continue
+ for (self.samplenum, (owr, pwr)) in data:
+# print ("DEBUG: sample = %d, owr = %d, pwr = %d, lnk_fall = %d, lnk_state = %s" % (self.samplenum, owr, pwr, self.lnk_fall, self.lnk_state))
# Data link layer
+
+ # Clear events.
+ self.lnk_event = "NONE"
+ # State machine.
if self.lnk_state == 'WAIT FOR FALLING EDGE':
# The start of a cycle is a falling edge.
- if (old_owr == 1 and owr == 0):
- # Save the sample number where the start bit begins.
- self.lnk_start = self.samplenum
+ if (owr == 0):
+ # Save the sample number for the falling edge.
+ self.lnk_fall = self.samplenum
# Go to waiting for sample time
- self.lnk_state = 'WAIT FOR SAMPLE'
- elif self.lnk_state == 'WAIT FOR SAMPLE':
+ self.lnk_state = 'WAIT FOR DATA SAMPLE'
+ elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
# Data should be sample one 'time unit' after a falling edge
- if (self.samplenum == self.lnk_start + self.time_base):
+ if (self.samplenum - self.lnk_fall == 0.5*self.time_base):
self.lnk_bit = owr & 0x1
- self.lnk_cnt = self.lnk_cnt + 1
- self.lnk_byte = (self.lnk_byte << 1) & self.lnk_bit
- self.lnk_state = 'WAIT FOR RISING EDGE'
+ self.lnk_event = "DATA BIT"
+ if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
+ else : self.lnk_state = 'WAIT FOR RISING EDGE'
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_LINK, ['BIT: %01x' % self.lnk_bit]])
elif self.lnk_state == 'WAIT FOR RISING EDGE':
# The end of a cycle is a rising edge.
- if (old_owr == 0 and owr == 1):
- # Data bit cycle length should be between 2*T and
- if (self.samplenum < self.lnk_start + 2*self.time_base):
- if (self.lnk_cnt == 8)
- self.put(self.startsample, self.samplenum - 1, self.out_proto, ['BYTE', self.lnk_byte])
- self.lnk_cnt = 0
- if (self.samplenum == self.lnk_start + 8*self.time_base):
- self.put(self.startsample, self.samplenum - 1, self.out_proto, ['RESET'])
-
- # Go to waiting for sample time
- self.lnk_state = 'WAIT FOR SAMPLE'
+ if (owr == 1):
+ # A reset cycle is longer than 8T.
+ if (self.samplenum - self.lnk_fall > 8*self.time_base):
+ # Save the sample number for the falling edge.
+ self.lnk_rise = self.samplenum
+ # Send a reset event to the next protocol layer.
+ self.lnk_event = "RESET"
+ self.lnk_state = "WAIT FOR PRESENCE DETECT"
+ self.put(self.lnk_fall, self.samplenum, self.out_proto, ['RESET'])
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_LINK , ['RESET']])
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['RESET']])
+ # Reset the timer.
+ self.lnk_fall = self.samplenum
+ # Otherwise this is assumed to be a data bit.
+ else :
+ self.lnk_state = "WAIT FOR FALLING EDGE"
+ elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
+ # Data should be sample one 'time unit' after a falling edge
+ if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
+ self.lnk_present = owr & 0x1
+ # Save the sample number for the falling edge.
+ if not (self.lnk_present) : self.lnk_fall = self.samplenum
+ # create presence detect event
+ #self.lnk_event = "PRESENCE DETECT"
+ if (self.lnk_present) : self.lnk_state = 'WAIT FOR FALLING EDGE'
+ else : self.lnk_state = 'WAIT FOR RISING EDGE'
+ present_str = "False" if self.lnk_present else "True"
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_LINK , ['PRESENCE: ' + present_str]])
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['PRESENCE: ' + present_str]])
+ else:
+ raise Exception('Invalid lnk_state: %d' % self.lnk_state)
- elif self.state_lnk == 'GET DATA BITS' : self.get_data_bits(owr)
- else : raise Exception('Invalid state: %d' % self.state)
+ # Network layer
+
+ # State machine.
+ if (self.lnk_event == "RESET"):
+ self.net_state = "COMMAND"
+ self.net_search = "P"
+ self.net_cnt = 0
+ elif (self.net_state == "IDLE"):
+ pass
+ elif (self.net_state == "COMMAND"):
+ if (self.collect_data(8)):
+# self.put(self.lnk_fall, self.samplenum,
+# self.out_proto, ['ROM COMMAND', self.net_data])
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM COMMAND: 0x%02x' % self.net_data]])
+ if (self.net_data == 0x33):
+ # READ ROM
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM COMMAND: \'READ ROM\'']])
+ self.net_state = "GET ROM"
+ elif (self.net_data == 0x0f):
+ # READ ROM TODO
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM COMMAND: \'READ ROM ???\'']])
+ self.net_state = "GET ROM"
+ elif (self.net_data == 0xcc):
+ # SKIP ROM
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM COMMAND: \'SKIP ROM\'']])
+ self.net_state = "IDLE"
+ self.trn_state = "COMMAND"
+ elif (self.net_data == 0x55):
+ # MATCH ROM
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM COMMAND: \'MATCH ROM\'']])
+ self.net_state = "GET ROM"
+ elif (self.net_data == 0xf0):
+ # SEARCH ROM
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM COMMAND: \'SEARCH ROM\'']])
+ self.net_state = "SEARCH ROM"
+ elif (self.net_data == 0x3c):
+ # OVERDRIVE SKIP ROM
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM COMMAND: \'OVERDRIVE SKIP ROM\'']])
+ self.net_state = "IDLE"
+ self.trn_state = "COMMAND"
+ elif (self.net_data == 0x69):
+ # OVERDRIVE MATCH ROM
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM COMMAND: \'OVERDRIVE MATCH ROM\'']])
+ self.net_state = "GET ROM"
+ elif (self.net_state == "GET ROM"):
+ # family code (1B) + serial number (6B) + CRC (1B)
+ if (self.collect_data((1+6+1)*8)):
+ self.net_rom = self.net_data & 0xffffffffffffffff
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM: 0x%016x' % self.net_rom]])
+ self.net_state = "IDLE"
+ self.trn_state = "COMMAND"
+ elif (self.net_state == "SEARCH ROM"):
+ # family code (1B) + serial number (6B) + CRC (1B)
+ if (self.collect_search((1+6+1)*8)):
+ self.net_rom = self.net_data & 0xffffffffffffffff
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK, ['ROM: 0x%016x' % self.net_rom]])
+ self.net_state = "IDLE"
+ self.trn_state = "COMMAND"
+ else:
+ raise Exception('Invalid net_state: %s' % self.net_state)
- # Save current RX/TX values for the next round.
- self.oldbit = owr
+ # Transport layer
+
+ # State machine.
+ if (self.lnk_event == "RESET"):
+ self.trn_state = "IDLE"
+ elif (self.trn_state == "IDLE"):
+ pass
+ elif (self.trn_state == "COMMAND"):
+ if (self.collect_data(8)):
+# self.put(self.lnk_fall, self.samplenum, self.out_proto, ['FUNCTION COMMAND', self.net_data])
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK , ['FUNCTION COMMAND: 0x%02x' % self.net_data]])
+ self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_TRANSFER, ['FUNCTION COMMAND: 0x%02x' % self.net_data]])
+ if (self.net_data == 0x48):
+ # COPY SCRATCHPAD
+ self.trn_state = "TODO"
+ elif (self.net_data == 0x4e):
+ # WRITE SCRATCHPAD
+ self.trn_state = "TODO"
+ elif (self.net_data == 0xbe):
+ # READ SCRATCHPAD
+ self.trn_state = "TODO"
+ elif (self.net_data == 0xb8):
+ # RECALL E2
+ self.trn_state = "TODO"
+ elif (self.net_data == 0xb4):
+ # READ POWER SUPPLY
+ self.trn_state = "TODO"
+ else:
+ # unsupported commands
+ self.trn_state = "TODO"
+ elif (self.trn_state == "TODO"):
+# self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_NETWORK , ['TODO unsupported transfer state: %s' % self.trn_state]])
+# self.put(self.lnk_fall, self.samplenum, self.out_ann, [ANN_TRANSFER, ['TODO unsupported transfer state: %s' % self.trn_state]])
+ pass
+ else:
+ raise Exception('Invalid trn_state: %s' % self.trn_state)
+ # Link/Network layer data collector
+ def collect_data (self, length):
+ if (self.lnk_event == "DATA BIT"):
+ #print ("DEBUG: BIT=%d t0=%d t+=%d" % (self.lnk_bit, self.lnk_fall, self.samplenum))
+ self.net_data = self.net_data & ~(1 << self.net_cnt) | (self.lnk_bit << self.net_cnt)
+ self.net_cnt = self.net_cnt + 1
+ if (self.net_cnt == length):
+ self.net_data = self.net_data & ((1<<length)-1)
+ self.net_cnt = 0
+ return (1)
+ else:
+ return (0)
+ else:
+ return (0)
+
+ # Link/Network layer search collector
+ def collect_search (self, length):
+ if (self.lnk_event == "DATA BIT"):
+ #print ("DEBUG: SEARCH=%s BIT=%d t0=%d t+=%d" % (self.net_search, self.lnk_bit, self.lnk_fall, self.samplenum))
+ if (self.net_search == "P"):
+ self.net_data_p = self.net_data_p & ~(1 << self.net_cnt) | (self.lnk_bit << self.net_cnt)
+ self.net_search = "N"
+ elif (self.net_search == "N"):
+ self.net_data_n = self.net_data_n & ~(1 << self.net_cnt) | (self.lnk_bit << self.net_cnt)
+ self.net_search = "D"
+ elif (self.net_search == "D"):
+ self.net_data = self.net_data & ~(1 << self.net_cnt) | (self.lnk_bit << self.net_cnt)
+ self.net_search = "P"
+ self.net_cnt = self.net_cnt + 1
+ if (self.net_cnt == length):
+ self.net_data_p = self.net_data_p & ((1<<length)-1)
+ self.net_data_n = self.net_data_n & ((1<<length)-1)
+ self.net_data = self.net_data & ((1<<length)-1)
+ self.net_search = "P"
+ self.net_cnt = 0
+ return (1)
+ else:
+ return (0)
+ else:
+ return (0)
projects / libsigrokdecode.git / blobdiff