##
import sigrokdecode as srd
+from common.srdhelper import bin2int
class Instruction(object):
IDCODE = 0x01
Instruction.FASTDATA: State.FASTDATA,
}
-def bin_to_int(s: str):
- return int('0b' + s, 2)
-
class RegData(object):
def __init__(self):
self.ss = None
self.data_in = None
self.data_out = None
self.write = False
- self.start_sample = 0
- self.end_sample = 0
+ self.ss = 0
+ self.es = 0
def __init__(self):
self.reset()
self.out_ann = self.register(srd.OUTPUT_ANN)
def select_reg(self, ir_value: int):
- if ir_value in ejtag_state_map:
- self.state = ejtag_state_map[ir_value]
- else:
- self.state = State.RESET
+ self.state = ejtag_state_map.get(ir_value, State.RESET)
def parse_pracc(self):
- control_in = bin_to_int(self.last_data['in']['data'][0])
- control_out = bin_to_int(self.last_data['out']['data'][0])
+ control_in = bin2int(self.last_data['in']['data'][0])
+ control_out = bin2int(self.last_data['out']['data'][0])
# Check if JTAG master acknowledges a pending PrAcc.
if not ((not (control_in & ControlReg.PRACC)) and \
(control_out & ControlReg.PRACC)):
return
- start_sample = self.pracc_state.start_sample
- end_sample = self.pracc_state.end_sample
+ ss, es = self.pracc_state.ss, self.pracc_state.es
pracc_write = (control_out & ControlReg.PRNW) != 0
- display_string = 'PrAcc: '
- display_string += 'Store' if pracc_write else 'Load/Fetch'
+ s = 'PrAcc: '
+ s += 'Store' if pracc_write else 'Load/Fetch'
if pracc_write:
if self.pracc_state.address_out != None:
- display_string += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
+ s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
if self.pracc_state.data_out != None:
- display_string += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out)
+ s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out)
else:
if self.pracc_state.address_out != None:
- display_string += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
+ s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
if self.pracc_state.data_in != None:
- display_string += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in)
+ s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in)
self.pracc_state.reset()
- display_data = [Ann.PRACC, [display_string]]
- self.put_at(start_sample, end_sample, display_data)
+ self.put_at(ss, es, [Ann.PRACC, [s]])
def parse_control_reg(self, ann):
reg_write = ann == Ann.CONTROL_FIELD_IN
control_bit_positions = []
- data_select = ''
-
- if reg_write:
- data_select = 'in'
- else:
- data_select = 'out'
+ data_select = 'in' if (reg_write) else 'out'
control_bit_positions = self.last_data[data_select]['data'][1]
control_data = self.last_data[data_select]['data'][0]
else:
value_descriptions = field[3][0]
- start_sample = control_bit_positions[start_bit][0]
- end_sample = control_bit_positions[end_bit][1]
+ ss = control_bit_positions[start_bit][0]
+ es = control_bit_positions[end_bit][1]
value_str = control_data[end_bit : start_bit + 1]
- value_index = bin_to_int(value_str)
+ value_index = bin2int(value_str)
short_desc = comment + ': ' + value_str
long_desc = value_descriptions[value_index] if len(value_descriptions) > value_index else '?'
- display_data = [ann, [short_desc, long_desc]]
- self.put_at(start_sample, end_sample, display_data)
+ self.put_at(ss, es, [ann, [long_desc, short_desc]])
def check_last_data(self):
if not hasattr(self, 'last_data'):
bitstring = val[0]
bit_sample_pos = val[1]
fastdata_state = bitstring[32]
- data = bin_to_int(bitstring[0:32])
+ data = bin2int(bitstring[0:32])
fastdata_bit_pos = bit_sample_pos[32]
data_pos = [bit_sample_pos[31][0], bit_sample_pos[0][1]]
- fastdata_sample_start, fastdata_sample_end = fastdata_bit_pos
- data_sample_start, data_sample_end = data_pos
+ ss_fastdata, es_fastdata = fastdata_bit_pos
+ ss_data, es_data = data_pos
display_data = [ann, ['0x{:08X}'.format(data)]]
spracc_display_data = []
elif ann == Ann.CONTROL_FIELD_OUT:
spracc_display_data = [ann, spracc_read_desc[int(fastdata_state)]]
- self.put_at(fastdata_sample_start, fastdata_sample_end, spracc_display_data)
- self.put_at(data_sample_start, data_sample_end, display_data)
+ self.put_at(ss_fastdata, es_fastdata, spracc_display_data)
+ self.put_at(ss_data, es_data, display_data)
def handle_dr_tdi(self, val):
- value = bin_to_int(val[0])
+ value = bin2int(val[0])
self.check_last_data()
self.last_data['in'] = {'ss': self.ss, 'es': self.es, 'data': val}
- self.pracc_state.start_sample = self.ss
- self.pracc_state.end_sample = self.es
+ self.pracc_state.ss, self.pracc_state.es = self.ss, self.es
if self.state == State.ADDRESS:
self.pracc_state.address_in = value
self.handle_fastdata(val, Ann.CONTROL_FIELD_IN)
def handle_dr_tdo(self, val):
- value = bin_to_int(val[0])
+ value = bin2int(val[0])
self.check_last_data()
self.last_data['out'] = {'ss': self.ss, 'es': self.es, 'data': val}
if self.state == State.ADDRESS:
self.handle_fastdata(val, Ann.CONTROL_FIELD_OUT)
def handle_ir_tdi(self, val):
- code = bin_to_int(val[0])
+ code = bin2int(val[0])
hex = '0x{:02X}'.format(code)
if code in ejtag_insn:
# Format instruction name.
s_short = insn[0]
s_long = insn[0] + ': ' + insn[1] + ' (' + hex + ')'
# Display it and select data register.
- self.put_current([Ann.INSTRUCTION, [s_short, s_long]])
+ self.put_current([Ann.INSTRUCTION, [s_long, s_short]])
else:
self.put_current([Ann.INSTRUCTION, [hex, 'IR TDI ({})'.format(hex)]])
self.select_reg(code)
projects / libsigrokdecode.git / blobdiff