##
## This file is part of the libsigrokdecode project.
##
-## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
-# JTAG protocol decoder
-
import sigrokdecode as srd
+'''
+OUTPUT_PYTHON format:
+
+Packet:
+[<ptype>, <pdata>]
+
+<ptype>:
+ - 'NEW STATE': <pdata> is the new state of the JTAG state machine.
+ Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
+ 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
+ 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
+ 'EXIT2-IR', 'UPDATE-IR'.
+ - 'IR TDI': Bitstring that was clocked into the IR register.
+ - 'IR TDO': Bitstring that was clocked out of the IR register.
+ - 'DR TDI': Bitstring that was clocked into the DR register.
+ - 'DR TDO': Bitstring that was clocked out of the DR register.
+
+All bitstrings are a list consisting of two items. The first is a sequence
+of '1' and '0' characters (the right-most character is the LSB. Example:
+'01110001', where 1 is the LSB). The second item is a list of ss/es values
+for each bit that is in the bitstring.
+'''
+
+jtag_states = [
+ # Intro "tree"
+ 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
+ # DR "tree"
+ 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
+ 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
+ # IR "tree"
+ 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
+ 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
+]
+
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 3
id = 'jtag'
name = 'JTAG'
longname = 'Joint Test Action Group (IEEE 1149.1)'
license = 'gplv2+'
inputs = ['logic']
outputs = ['jtag']
- probes = [
+ channels = (
{'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
{'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
{'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
{'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
- ]
- optional_probes = [
+ )
+ optional_channels = (
{'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
{'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
{'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
- ]
- options = {}
- annotations = [
- ['Text', 'Human-readable text'],
- ]
-
- def __init__(self, **kwargs):
+ )
+ annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
+ ('bit-tdi', 'Bit (TDI)'),
+ ('bit-tdo', 'Bit (TDO)'),
+ ('bitstring-tdi', 'Bitstring (TDI)'),
+ ('bitstring-tdo', 'Bitstring (TDO)'),
+ )
+ annotation_rows = (
+ ('bits-tdi', 'Bits (TDI)', (16,)),
+ ('bits-tdo', 'Bits (TDO)', (17,)),
+ ('bitstrings-tdi', 'Bitstring (TDI)', (18,)),
+ ('bitstrings-tdo', 'Bitstring (TDO)', (19,)),
+ ('states', 'States', tuple(range(15 + 1))),
+ )
+
+ def __init__(self):
# self.state = 'TEST-LOGIC-RESET'
self.state = 'RUN-TEST/IDLE'
self.oldstate = None
- self.oldpins = (-1, -1, -1, -1)
- self.oldtck = -1
self.bits_tdi = []
self.bits_tdo = []
+ self.bits_samplenums_tdi = []
+ self.bits_samplenums_tdo = []
+ self.ss_item = self.es_item = None
+ self.ss_bitstring = self.es_bitstring = None
+ self.saved_item = None
+ self.first = True
+ self.first_bit = True
def start(self):
- self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
+ def putx(self, data):
+ self.put(self.ss_item, self.es_item, self.out_ann, data)
+
+ def putp(self, data):
+ self.put(self.ss_item, self.es_item, self.out_python, data)
+
+ def putx_bs(self, data):
+ self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)
+
+ def putp_bs(self, data):
+ self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)
+
def advance_state_machine(self, tms):
self.oldstate = self.state
elif self.state == 'UPDATE-IR':
self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
- else:
- raise Exception('Invalid state: %s' % self.state)
+ def handle_rising_tck_edge(self, pins):
+ (tdi, tdo, tck, tms, trst, srst, rtck) = pins
- def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
# Rising TCK edges always advance the state machine.
self.advance_state_machine(tms)
- # Output the state we just switched to.
- self.put(self.ss, self.es, self.out_ann,
- [0, ['New state: %s' % self.state]])
- self.put(self.ss, self.es, self.out_proto,
- ['NEW STATE', self.state])
+ if self.first:
+ # Save the start sample and item for later (no output yet).
+ self.ss_item = self.samplenum
+ self.first = False
+ else:
+ # Output the saved item (from the last CLK edge to the current).
+ self.es_item = self.samplenum
+ # Output the old state (from last rising TCK edge to current one).
+ self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
+ self.putp(['NEW STATE', self.state])
+
+ # Upon SHIFT-IR/SHIFT-DR collect the current TDI/TDO values.
+ if self.state.startswith('SHIFT-'):
+ if self.first_bit:
+ self.ss_bitstring = self.samplenum
+ self.first_bit = False
+ else:
+ self.putx([16, [str(self.bits_tdi[0])]])
+ self.putx([17, [str(self.bits_tdo[0])]])
+ # Use self.samplenum as ES of the previous bit.
+ self.bits_samplenums_tdi[0][1] = self.samplenum
+ self.bits_samplenums_tdo[0][1] = self.samplenum
- # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR,
- # collect the current TDI/TDO values (upon rising TCK edge).
- if self.state.startswith('SHIFT-') and self.oldstate == self.state:
self.bits_tdi.insert(0, tdi)
self.bits_tdo.insert(0, tdo)
- # TODO: ANN/PROTO output.
- # self.put(self.ss, self.es, self.out_ann,
- # [0, ['TDI add: ' + str(tdi)]])
- # self.put(self.ss, self.es, self.out_ann,
- # [0, ['TDO add: ' + str(tdo)]])
+
+ # Use self.samplenum as SS of the current bit.
+ self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
+ self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
# Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
if self.oldstate.startswith('SHIFT-') and \
self.state.startswith('EXIT1-'):
+ self.es_bitstring = self.samplenum
+
t = self.state[-2:] + ' TDI'
b = ''.join(map(str, self.bits_tdi))
h = ' (0x%x' % int('0b' + b, 2) + ')'
s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
- self.put(self.ss, self.es, self.out_ann, [0, [s]])
- self.put(self.ss, self.es, self.out_proto, [t, b])
+ self.putx_bs([18, [s]])
+ self.bits_samplenums_tdi[0][1] = self.samplenum # ES of last bit.
+ self.putp_bs([t, [b, self.bits_samplenums_tdi]])
+ self.putx([16, [str(self.bits_tdi[0])]]) # Last bit.
self.bits_tdi = []
+ self.bits_samplenums_tdi = []
t = self.state[-2:] + ' TDO'
b = ''.join(map(str, self.bits_tdo))
h = ' (0x%x' % int('0b' + b, 2) + ')'
s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
- self.put(self.ss, self.es, self.out_ann, [0, [s]])
- self.put(self.ss, self.es, self.out_proto, [t, b])
+ self.putx_bs([19, [s]])
+ self.bits_samplenums_tdo[0][1] = self.samplenum # ES of last bit.
+ self.putp_bs([t, [b, self.bits_samplenums_tdo]])
+ self.putx([17, [str(self.bits_tdo[0])]]) # Last bit.
self.bits_tdo = []
+ self.bits_samplenums_tdo = []
- def decode(self, ss, es, data):
- for (samplenum, pins) in data:
-
- # If none of the pins changed, there's nothing to do.
- if self.oldpins == pins:
- continue
-
- # Store current pin values for the next round.
- self.oldpins = pins
-
- # Get individual pin values into local variables.
- # Unused probes will have a value of > 1.
- (tdi, tdo, tck, tms, trst, srst, rtck) = pins
-
- # We only care about TCK edges (either rising or falling).
- if (self.oldtck == tck):
- continue
-
- # Store start/end sample for later usage.
- self.ss, self.es = ss, es
-
- # self.put(self.ss, self.es, self.out_ann,
- # [0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \
- # % (tdi, tdo, tck, tms)]])
+ self.first_bit = True
- if (self.oldtck == 0 and tck == 1):
- self.handle_rising_tck_edge(tdi, tdo, tck, tms)
+ self.ss_bitstring = self.samplenum
- self.oldtck = tck
+ self.ss_item = self.samplenum
+ def decode(self):
+ while True:
+ # Wait for a rising edge on TCK.
+ self.handle_rising_tck_edge(self.wait({2: 'r'}))
projects / libsigrokdecode.git / blobdiff