##
## This file is part of the libsigrokdecode project.
##
-## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# I2C protocol decoder
-
# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
-# TODO: Handle clock stretching.
-# TODO: Handle combined messages / repeated START.
-# TODO: Implement support for 7bit and 10bit slave addresses.
+# TODO: Implement support for 10bit slave addresses.
# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
# TODO: Implement support for detecting various bus errors.
-# TODO: I2C address of slaves.
-# TODO: Handle multiple different I2C devices on same bus
-# -> we need to decode multiple protocols at the same time.
import sigrokdecode as srd
-# Annotation feed formats
-ANN_SHIFTED = 0
-ANN_SHIFTED_SHORT = 1
-ANN_RAW = 2
-
-# Values are verbose and short annotation, respectively.
+'''
+OUTPUT_PYTHON format:
+
+I²C packet:
+[<cmd>, <data>]
+
+<cmd> is one of:
+ - 'START' (START condition)
+ - 'START REPEAT' (Repeated START condition)
+ - 'ADDRESS READ' (Slave address, read)
+ - 'ADDRESS WRITE' (Slave address, write)
+ - 'DATA READ' (Data, read)
+ - 'DATA WRITE' (Data, write)
+ - 'STOP' (STOP condition)
+ - 'ACK' (ACK bit)
+ - 'NACK' (NACK bit)
+ - 'BITS' (<data>: list of data/address bits and their ss/es numbers)
+
+<data> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
+command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
+For example, a slave address field could be 0x51 (instead of 0xa2).
+For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <data> is None.
+'''
+
+# CMD: [annotation-type-index, long annotation, short annotation]
proto = {
- 'START': ['START', 'S'],
- 'START REPEAT': ['START REPEAT', 'Sr'],
- 'STOP': ['STOP', 'P'],
- 'ACK': ['ACK', 'A'],
- 'NACK': ['NACK', 'N'],
- 'ADDRESS READ': ['ADDRESS READ', 'AR'],
- 'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'],
- 'DATA READ': ['DATA READ', 'DR'],
- 'DATA WRITE': ['DATA WRITE', 'DW'],
+ 'START': [0, 'Start', 'S'],
+ 'START REPEAT': [1, 'Start repeat', 'Sr'],
+ 'STOP': [2, 'Stop', 'P'],
+ 'ACK': [3, 'ACK', 'A'],
+ 'NACK': [4, 'NACK', 'N'],
+ 'BIT': [5, 'Bit', 'B'],
+ 'ADDRESS READ': [6, 'Address read', 'AR'],
+ 'ADDRESS WRITE': [7, 'Address write', 'AW'],
+ 'DATA READ': [8, 'Data read', 'DR'],
+ 'DATA WRITE': [9, 'Data write', 'DW'],
}
class Decoder(srd.Decoder):
api_version = 1
id = 'i2c'
- name = 'I2C'
+ name = 'I²C'
longname = 'Inter-Integrated Circuit'
desc = 'Two-wire, multi-master, serial bus.'
license = 'gplv2+'
{'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
]
optional_probes = []
- options = {
- 'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
- }
+ options = (
+ {'id': 'address_format', 'desc': 'Displayed slave address format',
+ 'default': 'shifted', 'values': ('shifted', 'unshifted')},
+ )
annotations = [
- # ANN_SHIFTED
- ['7-bit shifted hex',
- 'Read/write bit shifted out from the 8-bit I2C slave address'],
- # ANN_SHIFTED_SHORT
- ['7-bit shifted hex (short)',
- 'Read/write bit shifted out from the 8-bit I2C slave address'],
- # ANN_RAW
- ['Raw hex', 'Unaltered raw data'],
+ ['start', 'Start condition'],
+ ['repeat-start', 'Repeat start condition'],
+ ['stop', 'Stop condition'],
+ ['ack', 'ACK'],
+ ['nack', 'NACK'],
+ ['bit', 'Data/address bit'],
+ ['address-read', 'Address read'],
+ ['address-write', 'Address write'],
+ ['data-read', 'Data read'],
+ ['data-write', 'Data write'],
+ ['warnings', 'Human-readable warnings'],
]
+ annotation_rows = (
+ ('bits', 'Bits', (5,)),
+ ('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 6, 7, 8, 9)),
+ ('warnings', 'Warnings', (10,)),
+ )
+ binary = (
+ ('address-read', 'Address read'),
+ ('address-write', 'Address write'),
+ ('data-read', 'Data read'),
+ ('data-write', 'Data write'),
+ )
def __init__(self, **kwargs):
- self.startsample = -1
+ self.samplerate = None
+ self.ss = self.es = self.byte_ss = -1
self.samplenum = None
self.bitcount = 0
self.databyte = 0
self.wr = -1
self.is_repeat_start = 0
self.state = 'FIND START'
- self.oldscl = 1
- self.oldsda = 1
- self.oldpins = (1, 1)
+ self.oldscl = self.oldsda = 1
+ self.oldpins = [1, 1]
+ self.pdu_start = None
+ self.pdu_bits = 0
+ self.bits = []
+
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
+
+ def start(self):
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_binary = self.register(srd.OUTPUT_BINARY)
+ self.out_bitrate = self.register(srd.OUTPUT_META,
+ meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit'))
+
+ def putx(self, data):
+ self.put(self.ss, self.es, self.out_ann, data)
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
+ def putp(self, data):
+ self.put(self.ss, self.es, self.out_python, data)
- def report(self):
- pass
+ def putb(self, data):
+ self.put(self.ss, self.es, self.out_binary, data)
def is_start_condition(self, scl, sda):
# START condition (S): SDA = falling, SCL = high
return False
def found_start(self, scl, sda):
- self.startsample = self.samplenum
-
+ self.ss, self.es = self.samplenum, self.samplenum
+ self.pdu_start = self.samplenum
+ self.pdu_bits = 0
cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
- self.put(self.out_proto, [cmd, None])
- self.put(self.out_ann, [ANN_SHIFTED, [proto[cmd][0]]])
- self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[cmd][1]]])
-
+ self.putp([cmd, None])
+ self.putx([proto[cmd][0], proto[cmd][1:]])
self.state = 'FIND ADDRESS'
self.bitcount = self.databyte = 0
self.is_repeat_start = 1
self.wr = -1
+ self.bits = []
# Gather 8 bits of data plus the ACK/NACK bit.
def found_address_or_data(self, scl, sda):
self.databyte <<= 1
self.databyte |= sda
+ # Remember the start of the first data/address bit.
if self.bitcount == 0:
- self.startsample = self.samplenum
+ self.byte_ss = self.samplenum
+
+ # Store individual bits and their start/end samplenumbers.
+ # In the list, index 0 represents the LSB (I²C transmits MSB-first).
+ self.bits.insert(0, [sda, self.samplenum, self.samplenum])
+ if self.bitcount > 0:
+ self.bits[1][2] = self.samplenum
+ if self.bitcount == 7:
+ self.bitwidth = self.bits[1][2] - self.bits[2][2]
+ self.bits[0][2] += self.bitwidth
# Return if we haven't collected all 8 + 1 bits, yet.
- self.bitcount += 1
- if self.bitcount != 8:
+ if self.bitcount < 7:
+ self.bitcount += 1
return
- # We triggered on the ACK/NACK bit, but won't report that until later.
- self.startsample -= 1
-
- # Send raw output annotation before we start shifting out
- # read/write and ACK/NACK bits.
- self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
-
+ d = self.databyte
if self.state == 'FIND ADDRESS':
# The READ/WRITE bit is only in address bytes, not data bytes.
self.wr = 0 if (self.databyte & 1) else 1
- d = self.databyte >> 1
- elif self.state == 'FIND DATA':
- d = self.databyte
+ if self.options['address_format'] == 'shifted':
+ d = d >> 1
+ bin_class = -1
if self.state == 'FIND ADDRESS' and self.wr == 1:
cmd = 'ADDRESS WRITE'
+ bin_class = 1
elif self.state == 'FIND ADDRESS' and self.wr == 0:
cmd = 'ADDRESS READ'
+ bin_class = 0
elif self.state == 'FIND DATA' and self.wr == 1:
cmd = 'DATA WRITE'
+ bin_class = 3
elif self.state == 'FIND DATA' and self.wr == 0:
cmd = 'DATA READ'
+ bin_class = 2
+
+ self.ss, self.es = self.byte_ss, self.samplenum + self.bitwidth
+
+ self.putp(['BITS', self.bits])
+ self.putp([cmd, d])
+
+ self.putb((bin_class, bytes([d])))
- self.put(self.out_proto, [cmd, d])
- self.put(self.out_ann, [ANN_SHIFTED, [proto[cmd][0], '0x%02x' % d]])
- self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[cmd][1], '0x%02x' % d]])
+ for bit in self.bits:
+ self.put(bit[1], bit[2], self.out_ann, [5, ['%d' % bit[0]]])
+
+ if cmd.startswith('ADDRESS'):
+ self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
+ w = ['Write', 'Wr', 'W'] if self.wr else ['Read', 'Rd', 'R']
+ self.putx([proto[cmd][0], w])
+ self.ss, self.es = self.byte_ss, self.samplenum
+
+ self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
+ '%s: %02X' % (proto[cmd][2], d), '%02X' % d]])
# Done with this packet.
- self.startsample = -1
self.bitcount = self.databyte = 0
+ self.bits = []
self.state = 'FIND ACK'
def get_ack(self, scl, sda):
- self.startsample = self.samplenum
- ack_bit = 'NACK' if (sda == 1) else 'ACK'
- self.put(self.out_proto, [ack_bit, None])
- self.put(self.out_ann, [ANN_SHIFTED, [proto[ack_bit][0]]])
- self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[ack_bit][1]]])
+ self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
+ cmd = 'NACK' if (sda == 1) else 'ACK'
+ self.putp([cmd, None])
+ self.putx([proto[cmd][0], proto[cmd][1:]])
# There could be multiple data bytes in a row, so either find
# another data byte or a STOP condition next.
self.state = 'FIND DATA'
def found_stop(self, scl, sda):
- self.startsample = self.samplenum
- self.put(self.out_proto, ['STOP', None])
- self.put(self.out_ann, [ANN_SHIFTED, [proto['STOP'][0]]])
- self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto['STOP'][1]]])
-
+ # Meta bitrate
+ elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1)
+ bitrate = int(1 / elapsed * self.pdu_bits)
+ self.put(self.byte_ss, self.samplenum, self.out_bitrate, bitrate)
+
+ cmd = 'STOP'
+ self.ss, self.es = self.samplenum, self.samplenum
+ self.putp([cmd, None])
+ self.putx([proto[cmd][0], proto[cmd][1:]])
self.state = 'FIND START'
self.is_repeat_start = 0
self.wr = -1
-
- def put(self, output_id, data):
- # Inject sample range into the call up to sigrok.
- super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)
+ self.bits = []
def decode(self, ss, es, data):
+ if self.samplerate is None:
+ raise Exception("Cannot decode without samplerate.")
for (self.samplenum, pins) in data:
# Ignore identical samples early on (for performance reasons).
continue
self.oldpins, (scl, sda) = pins, pins
- # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
+ self.pdu_bits += 1
# State machine.
if self.state == 'FIND START':
raise Exception('Invalid state: %s' % self.state)
# Save current SDA/SCL values for the next round.
- self.oldscl = scl
- self.oldsda = sda
+ self.oldscl, self.oldsda = scl, sda
projects / libsigrokdecode.git / blobdiff