srd: All PDs: Various fixes, cosmetics.

[libsigrokdecode.git] / decoders / i2c / i2c.py

diff --git a/decoders/i2c/i2c.py b/decoders/i2c/i2c.py
index 4352c36246a3edb117c03ae49c2103c7ab4ae693..816fd790baa33fb4ca0d2091390911ad4b91596a 100644 (file)
--- a/decoders/i2c/i2c.py
+++ b/decoders/i2c/i2c.py
@@ -129,6 +129,7 @@ class Decoder(srd.Decoder):
         {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
         {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
     ]
+    extra_probes = []
     options = {
         'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
     }
@@ -158,6 +159,9 @@ class Decoder(srd.Decoder):
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
         self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
 
+    def report(self):
+        pass
+
     def is_start_condition(self, scl, sda):
         # START condition (S): SDA = falling, SCL = high
         if (self.oldsda == 1 and sda == 0) and scl == 1:
@@ -290,8 +294,7 @@ class Decoder(srd.Decoder):
                 elif self.is_stop_condition(scl, sda):
                     self.found_stop(scl, sda)
             else:
-                # Shouldn't happen.
-                raise Exception("unknown state %d" % self.STATE)
+                raise Exception('Invalid state %d' % self.STATE)
 
             # Save current SDA/SCL values for the next round.
             self.oldscl = scl