# 'signals': [{'SCL': }]}
#
+import sigrok
+
+# symbols for i2c decoders up the stack
+START = 1
+START_REPEAT = 2
+STOP = 3
+ACK = 4
+NACK = 5
+ADDRESS_READ = 6
+ADDRESS_WRITE = 7
+DATA_READ = 8
+DATA_WRITE = 9
+
+# States
+FIND_START = 0
+FIND_ADDRESS = 1
+FIND_DATA = 2
+
class Sample():
def __init__(self, data):
self.data = data
def probe(self, probe):
- s = ord(self.data[probe / 8]) & (1 << (probe % 8))
+ s = self.data[probe / 8] & (1 << (probe % 8))
return True if s else False
def sampleiter(data, unitsize):
for i in range(0, len(data), unitsize):
yield(Sample(data[i:i+unitsize]))
-class Decoder():
+class Decoder(sigrok.Decoder):
+ id = 'i2c'
name = 'I2C'
longname = 'Inter-Integrated Circuit (I2C) bus'
desc = 'I2C is a two-wire, multi-master, serial bus.'
def __init__(self, **kwargs):
self.probes = Decoder.probes.copy()
+ self.output_protocol = None
+ self.output_annotation = None
# TODO: Don't hardcode the number of channels.
self.channels = 8
self.startsample = -1
self.is_repeat_start = 0
- self.FIND_START, self.FIND_ADDRESS, self.FIND_DATA = range(3)
- self.state = self.FIND_START
+ self.state = FIND_START
# Get the channel/probe number of the SCL/SDA signals.
self.scl_bit = self.probes['scl']['ch']
def start(self, metadata):
self.unitsize = metadata["unitsize"]
+ self.output_protocol = self.output_new(2)
+ self.output_annotation = self.output_new(1)
def report(self):
pass
return True
return False
- def find_start(self, scl, sda):
- out = []
- # o = {'type': 'S', 'range': (self.samplenum, self.samplenum),
- # 'data': None, 'ann': None},
- o = (self.is_repeat_start == 1) and 'Sr' or 'S'
- out.append(o)
- self.state = self.FIND_ADDRESS
+ def found_start(self, scl, sda):
+ if self.is_repeat_start == 1:
+ out_proto = [ START_REPEAT ]
+ out_ann = [ "START REPEAT" ]
+ else:
+ out_proto = [ START ]
+ out_ann = [ "START" ]
+ self.put(self.output_protocol, out_proto)
+ self.put(self.output_annotation, out_ann)
+
+ self.state = FIND_ADDRESS
self.bitcount = self.databyte = 0
self.is_repeat_start = 1
self.wr = -1
- return out
- def find_address_or_data(self, scl, sda):
+ def found_address_or_data(self, scl, sda):
"""Gather 8 bits of data plus the ACK/NACK bit."""
- out = o = []
if self.startsample == -1:
self.startsample = self.samplenum
# We received 8 address/data bits and the ACK/NACK bit.
self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
- ack = (sda == 1) and 'N' or 'A'
-
- if self.state == self.FIND_ADDRESS:
+ if self.state == FIND_ADDRESS:
d = self.databyte & 0xfe
# The READ/WRITE bit is only in address bytes, not data bytes.
- self.wr = (self.databyte & 1) and 1 or 0
- elif self.state == self.FIND_DATA:
+ self.wr = 1 if (self.databyte & 1) else 0
+ elif self.state == FIND_DATA:
d = self.databyte
else:
# TODO: Error?
pass
- # o = {'type': self.state,
- # 'range': (self.startsample, self.samplenum - 1),
- # 'data': d, 'ann': None}
+ out_proto = []
+ out_ann = []
+ # TODO: Simplify.
+ if self.state == FIND_ADDRESS and self.wr == 1:
+ cmd = ADDRESS_WRITE
+ ann = 'ADDRESS WRITE'
+ elif self.state == FIND_ADDRESS and self.wr == 0:
+ cmd = ADDRESS_READ
+ ann = 'ADDRESS READ'
+ elif self.state == FIND_DATA and self.wr == 1:
+ cmd = DATA_WRITE
+ ann = 'DATA WRITE'
+ elif self.state == FIND_DATA and self.wr == 0:
+ cmd = DATA_READ
+ ann = 'DATA READ'
+ out_proto.append( [cmd, d] )
+ out_ann.append( ["%s" % ann, "0x%02x" % d] )
+
+ if sda == 1:
+ out_proto.append( [NACK] )
+ out_ann.append( ["NACK"] )
+ else:
+ out_proto.append( [ACK] )
+ out_ann.append( ["ACK"] )
- o = {'data': '0x%02x' % d}
+ self.put(self.output_protocol, out_proto)
+ self.put(self.output_annotation, out_ann)
- # TODO: Simplify.
- if self.state == self.FIND_ADDRESS and self.wr == 1:
- o['type'] = 'AW'
- elif self.state == self.FIND_ADDRESS and self.wr == 0:
- o['type'] = 'AR'
- elif self.state == self.FIND_DATA and self.wr == 1:
- o['type'] = 'DW'
- elif self.state == self.FIND_DATA and self.wr == 0:
- o['type'] = 'DR'
-
- out.append(o)
-
- # o = {'type': ack, 'range': (self.samplenum, self.samplenum),
- # 'data': None, 'ann': None}
- o = ack
- out.append(o)
self.bitcount = self.databyte = 0
self.startsample = -1
- if self.state == self.FIND_ADDRESS:
- self.state = self.FIND_DATA
- elif self.state == self.FIND_DATA:
+ if self.state == FIND_ADDRESS:
+ self.state = FIND_DATA
+ elif self.state == FIND_DATA:
# There could be multiple data bytes in a row.
# So, either find a STOP condition or another data byte next.
pass
- return out
+ def found_stop(self, scl, sda):
+ self.put(self.output_protocol, [ STOP ])
+ self.put(self.output_annotation, [ "STOP" ])
- def find_stop(self, scl, sda):
- out = o = []
-
- # o = {'type': 'P', 'range': (self.samplenum, self.samplenum),
- # 'data': None, 'ann': None},
- o = 'P'
- out.append(o)
- self.state = self.FIND_START
+ self.state = FIND_START
self.is_repeat_start = 0
self.wr = -1
- return out
-
- def decode(self, data):
- """I2C protocol decoder"""
+ def put(self, output_id, data):
+ timeoffset = self.timeoffset + ((self.samplenum - self.bitcount) * self.period)
+ if self.bitcount > 0:
+ duration = self.bitcount * self.period
+ else:
+ duration = self.period
+ print("**", timeoffset, duration)
+ super(Decoder, self).put(timeoffset, duration, output_id, data)
- out = []
- o = ack = d = ''
+ def decode(self, timeoffset, duration, data):
+ self.timeoffset = timeoffset
+ self.duration = duration
+ print("++", timeoffset, duration, len(data))
+ # duration of one bit in ps, only valid for this call to decode()
+ self.period = int(duration / len(data))
# We should accept a list of samples and iterate...
- for sample in sampleiter(data['data'], self.unitsize):
+ for sample in sampleiter(data, self.unitsize):
# TODO: Eliminate the need for ord().
s = ord(sample.data)
# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
# State machine.
- if self.state == self.FIND_START:
+ if self.state == FIND_START:
if self.is_start_condition(scl, sda):
- out += self.find_start(scl, sda)
- elif self.state == self.FIND_ADDRESS:
+ self.found_start(scl, sda)
+ elif self.state == FIND_ADDRESS:
if self.is_data_bit(scl, sda):
- out += self.find_address_or_data(scl, sda)
- elif self.state == self.FIND_DATA:
+ self.found_address_or_data(scl, sda)
+ elif self.state == FIND_DATA:
if self.is_data_bit(scl, sda):
- out += self.find_address_or_data(scl, sda)
+ self.found_address_or_data(scl, sda)
elif self.is_start_condition(scl, sda):
- out += self.find_start(scl, sda)
+ self.found_start(scl, sda)
elif self.is_stop_condition(scl, sda):
- out += self.find_stop(scl, sda)
+ self.found_stop(scl, sda)
else:
# TODO: Error?
pass
self.oldscl = scl
self.oldsda = sda
- if out != []:
- sigrok.put(out)
-
-import sigrok
projects / libsigrokdecode.git / blobdiff