##
## This file is part of the sigrok project.
##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
#
# START condition (S): SDA = falling, SCL = high
# Repeated START condition (Sr): same as S
+# Data bit sampling: SCL = rising
# STOP condition (P): SDA = rising, SCL = high
#
# All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
# Possible other events:
# - Error event in case protocol looks broken:
# [{'type': 'ERROR', 'range': (min, max),
-# 'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'},
+# 'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'},
# [{'type': 'ERROR', 'range': (min, max),
-# 'data': TODO, 'ann': 'TODO'},
+# 'data': TODO, 'ann': 'TODO'},
# - TODO: Make list of possible errors accessible as metadata?
#
# TODO: I2C address of slaves.
# 'signals': [{'SCL': }]}
#
-def decode(inbuf):
- """I2C protocol decoder"""
-
- # FIXME: Get the data in the correct format in the first place.
- inbuf = [ord(x) for x in inbuf]
-
- # FIXME: This should be passed in as metadata, not hardcoded here.
- metadata = {
- 'numchannels': 8,
- 'signals': {
- 'scl': {'ch': 5, 'name': 'SCL', 'desc': 'Serial clock line'},
- 'sda': {'ch': 7, 'name': 'SDA', 'desc': 'Serial data line'},
- },
- }
-
- out = []
- o = ack = d = ''
- bitcount = data = 0
- wr = startsample = -1
- IDLE, START, ADDRESS, DATA = range(4)
- state = IDLE
-
- # Get the channel/probe number of the SCL/SDA signals.
- scl_bit = metadata['signals']['scl']['ch']
- sda_bit = metadata['signals']['sda']['ch']
-
- # Get SCL/SDA bit values (0/1 for low/high) of the first sample.
- s = inbuf[0]
- oldscl = (s & (1 << scl_bit)) >> scl_bit
- oldsda = (s & (1 << sda_bit)) >> sda_bit
-
- # Loop over all samples.
- # TODO: Handle LAs with more/less than 8 channels.
- for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte...
- # Get SCL/SDA bit values (0/1 for low/high).
- scl = (s & (1 << scl_bit)) >> scl_bit
- sda = (s & (1 << sda_bit)) >> sda_bit
-
- # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
-
- # START condition (S): SDA = falling, SCL = high
- if (oldsda == 1 and sda == 0) and scl == 1:
- o = {'type': 'S', 'range': (samplenum, samplenum),
- 'data': None, 'ann': None},
- out.append(o)
- state = ADDRESS
- bitcount = data = 0
-
- # Data latching by transmitter: SCL = low
- elif (scl == 0):
- pass # TODO
-
- # Data sampling of receiver: SCL = rising
- elif (oldscl == 0 and scl == 1):
- if startsample == -1:
- startsample = samplenum
- bitcount += 1
-
- # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \
- # (samplenum, 8 - bitcount, sda))
-
- # Address and data are transmitted MSB-first.
- data <<= 1
- data |= sda
-
- if bitcount != 9:
- continue
-
- # We received 8 address/data bits and the ACK/NACK bit.
- data >>= 1 # Shift out unwanted ACK/NACK bit here.
- ack = (sda == 1) and 'N' or 'A'
- d = (state == ADDRESS) and (data & 0xfe) or data
- if state == ADDRESS:
- wr = (data & 1) and 1 or 0
- state = DATA
- o = {'type': state,
- 'range': (startsample, samplenum - 1),
- 'data': d, 'ann': None}
- if state == ADDRESS and wr == 1:
- o['type'] = 'AW'
- elif state == ADDRESS and wr == 0:
- o['type'] = 'AR'
- elif state == DATA and wr == 1:
- o['type'] = 'DW'
- elif state == DATA and wr == 0:
- o['type'] = 'DR'
- out.append(o)
- o = {'type': ack, 'range': (samplenum, samplenum),
- 'data': None, 'ann': None}
- out.append(o)
- bitcount = data = startsample = 0
- startsample = -1
-
- # STOP condition (P): SDA = rising, SCL = high
- elif (oldsda == 0 and sda == 1) and scl == 1:
- o = {'type': 'P', 'range': (samplenum, samplenum),
- 'data': None, 'ann': None},
- out.append(o)
- state = IDLE
- wr = -1
-
- # Save current SDA/SCL values for the next round.
- oldscl = scl
- oldsda = sda
-
- # FIXME: Just for testing...
- return str(out)
-
-def register():
- return {
- 'id': 'i2c',
- 'name': 'I2C',
- 'desc': 'Inter-Integrated Circuit (I2C) bus',
- 'inputformats': ['raw'],
- 'signalnames': {
- 'SCL': 'Serial clock line',
- 'SDA': 'Serial data line',
- },
- 'outputformats': ['i2c'],
- }
-
-# Use psyco (if available) as it results in huge performance improvements.
-try:
- import psyco
- psyco.bind(decode)
-except ImportError:
- pass
+import sigrok
+
+# States
+FIND_START = 0
+FIND_ADDRESS = 1
+FIND_DATA = 2
+
+class Sample():
+ def __init__(self, data):
+ self.data = data
+ def probe(self, probe):
+ s = ord(self.data[probe / 8]) & (1 << (probe % 8))
+ return True if s else False
+
+def sampleiter(data, unitsize):
+ for i in range(0, len(data), unitsize):
+ yield(Sample(data[i:i+unitsize]))
+
+class Decoder(sigrok.Decoder):
+ id = 'i2c'
+ name = 'I2C'
+ longname = 'Inter-Integrated Circuit (I2C) bus'
+ desc = 'I2C is a two-wire, multi-master, serial bus.'
+ longdesc = '...'
+ author = 'Uwe Hermann'
+ email = 'uwe@hermann-uwe.de'
+ license = 'gplv2+'
+ inputs = ['logic']
+ outputs = ['i2c']
+ probes = {
+ 'scl': {'ch': 0, 'name': 'SCL', 'desc': 'Serial clock line'},
+ 'sda': {'ch': 1, 'name': 'SDA', 'desc': 'Serial data line'},
+ }
+ options = {
+ 'address-space': ['Address space (in bits)', 7],
+ }
+
+ def __init__(self, **kwargs):
+ self.probes = Decoder.probes.copy()
+
+ # TODO: Don't hardcode the number of channels.
+ self.channels = 8
+
+ self.samplenum = 0
+ self.bitcount = 0
+ self.databyte = 0
+ self.wr = -1
+ self.startsample = -1
+ self.is_repeat_start = 0
+
+ self.state = FIND_START
+
+ # Get the channel/probe number of the SCL/SDA signals.
+ self.scl_bit = self.probes['scl']['ch']
+ self.sda_bit = self.probes['sda']['ch']
+
+ self.oldscl = None
+ self.oldsda = None
+
+ def start(self, metadata):
+ self.unitsize = metadata["unitsize"]
+
+ def report(self):
+ pass
+
+ def is_start_condition(self, scl, sda):
+ """START condition (S): SDA = falling, SCL = high"""
+ if (self.oldsda == 1 and sda == 0) and scl == 1:
+ return True
+ return False
+
+ def is_data_bit(self, scl, sda):
+ """Data sampling of receiver: SCL = rising"""
+ if self.oldscl == 0 and scl == 1:
+ return True
+ return False
+
+ def is_stop_condition(self, scl, sda):
+ """STOP condition (P): SDA = rising, SCL = high"""
+ if (self.oldsda == 0 and sda == 1) and scl == 1:
+ return True
+ return False
+
+ def find_start(self, scl, sda):
+ out = []
+ # o = {'type': 'S', 'range': (self.samplenum, self.samplenum),
+ # 'data': None, 'ann': None},
+ o = (self.is_repeat_start == 1) and 'Sr' or 'S'
+ out.append(o)
+ self.state = FIND_ADDRESS
+ self.bitcount = self.databyte = 0
+ self.is_repeat_start = 1
+ self.wr = -1
+ return out
+
+ def find_address_or_data(self, scl, sda):
+ """Gather 8 bits of data plus the ACK/NACK bit."""
+ out = o = []
+
+ if self.startsample == -1:
+ self.startsample = self.samplenum
+ self.bitcount += 1
+
+ # Address and data are transmitted MSB-first.
+ self.databyte <<= 1
+ self.databyte |= sda
+
+ # Return if we haven't collected all 8 + 1 bits, yet.
+ if self.bitcount != 9:
+ return []
+
+ # We received 8 address/data bits and the ACK/NACK bit.
+ self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
+
+ ack = (sda == 1) and 'N' or 'A'
+
+ if self.state == FIND_ADDRESS:
+ d = self.databyte & 0xfe
+ # The READ/WRITE bit is only in address bytes, not data bytes.
+ self.wr = (self.databyte & 1) and 1 or 0
+ elif self.state == FIND_DATA:
+ d = self.databyte
+ else:
+ # TODO: Error?
+ pass
+
+ # o = {'type': self.state,
+ # 'range': (self.startsample, self.samplenum - 1),
+ # 'data': d, 'ann': None}
+
+ o = {'data': '0x%02x' % d}
+
+ # TODO: Simplify.
+ if self.state == FIND_ADDRESS and self.wr == 1:
+ o['type'] = 'AW'
+ elif self.state == FIND_ADDRESS and self.wr == 0:
+ o['type'] = 'AR'
+ elif self.state == FIND_DATA and self.wr == 1:
+ o['type'] = 'DW'
+ elif self.state == FIND_DATA and self.wr == 0:
+ o['type'] = 'DR'
+
+ out.append(o)
+
+ # o = {'type': ack, 'range': (self.samplenum, self.samplenum),
+ # 'data': None, 'ann': None}
+ o = ack
+ out.append(o)
+ self.bitcount = self.databyte = 0
+ self.startsample = -1
+
+ if self.state == FIND_ADDRESS:
+ self.state = FIND_DATA
+ elif self.state == FIND_DATA:
+ # There could be multiple data bytes in a row.
+ # So, either find a STOP condition or another data byte next.
+ pass
+
+ return out
+
+ def find_stop(self, scl, sda):
+ out = o = []
+
+ # o = {'type': 'P', 'range': (self.samplenum, self.samplenum),
+ # 'data': None, 'ann': None},
+ o = 'P'
+ out.append(o)
+ self.state = FIND_START
+ self.is_repeat_start = 0
+ self.wr = -1
+
+ return out
+
+ def decode(self, data):
+ """I2C protocol decoder"""
+
+ out = []
+ o = ack = d = ''
+
+ # We should accept a list of samples and iterate...
+ for sample in sampleiter(data['data'], self.unitsize):
+
+ # TODO: Eliminate the need for ord().
+ s = ord(sample.data)
+
+ # TODO: Start counting at 0 or 1?
+ self.samplenum += 1
+
+ # First sample: Save SCL/SDA value.
+ if self.oldscl == None:
+ # Get SCL/SDA bit values (0/1 for low/high) of the first sample.
+ self.oldscl = (s & (1 << self.scl_bit)) >> self.scl_bit
+ self.oldsda = (s & (1 << self.sda_bit)) >> self.sda_bit
+ continue
+
+ # Get SCL/SDA bit values (0/1 for low/high).
+ scl = (s & (1 << self.scl_bit)) >> self.scl_bit
+ sda = (s & (1 << self.sda_bit)) >> self.sda_bit
+
+ # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
+
+ # State machine.
+ if self.state == FIND_START:
+ if self.is_start_condition(scl, sda):
+ out += self.find_start(scl, sda)
+ elif self.state == FIND_ADDRESS:
+ if self.is_data_bit(scl, sda):
+ out += self.find_address_or_data(scl, sda)
+ elif self.state == FIND_DATA:
+ if self.is_data_bit(scl, sda):
+ out += self.find_address_or_data(scl, sda)
+ elif self.is_start_condition(scl, sda):
+ out += self.find_start(scl, sda)
+ elif self.is_stop_condition(scl, sda):
+ out += self.find_stop(scl, sda)
+ else:
+ # TODO: Error?
+ pass
+
+ # Save current SDA/SCL values for the next round.
+ self.oldscl = scl
+ self.oldsda = sda
+
+ if out != []:
+ self.put(out)
projects / libsigrokdecode.git / blobdiff