srd: Update decoders to changed API.

[libsigrokdecode.git] / decoders / i2c.py

diff --git a/decoders/i2c.py b/decoders/i2c.py
index 4b138250aaedc1af213f8161332f7094060d70ee..2b3b8756f7ad8fe4cee12f0c154aebc55e064694 100644 (file)
--- a/decoders/i2c.py
+++ b/decoders/i2c.py
@@ -126,6 +126,13 @@
 #  'signals': [{'SCL': }]}
 #
 
+import sigrok
+
+# States
+FIND_START = 0
+FIND_ADDRESS = 1
+FIND_DATA = 2
+
 class Sample():
     def __init__(self, data):
         self.data = data
@@ -137,7 +144,8 @@ def sampleiter(data, unitsize):
     for i in range(0, len(data), unitsize):
         yield(Sample(data[i:i+unitsize]))
 
-class Decoder():
+class Decoder(sigrok.Decoder):
+    id = 'i2c'
     name = 'I2C'
     longname = 'Inter-Integrated Circuit (I2C) bus'
     desc = 'I2C is a two-wire, multi-master, serial bus.'
@@ -168,8 +176,7 @@ class Decoder():
         self.startsample = -1
         self.is_repeat_start = 0
 
-        self.FIND_START, self.FIND_ADDRESS, self.FIND_DATA = range(3)
-        self.state = self.FIND_START
+        self.state = FIND_START
 
         # Get the channel/probe number of the SCL/SDA signals.
         self.scl_bit = self.probes['scl']['ch']
@@ -208,7 +215,7 @@ class Decoder():
         #      'data': None, 'ann': None},
         o = (self.is_repeat_start == 1) and 'Sr' or 'S'
         out.append(o)
-        self.state = self.FIND_ADDRESS
+        self.state = FIND_ADDRESS
         self.bitcount = self.databyte = 0
         self.is_repeat_start = 1
         self.wr = -1
@@ -235,11 +242,11 @@ class Decoder():
 
         ack = (sda == 1) and 'N' or 'A'
 
-        if self.state == self.FIND_ADDRESS:
+        if self.state == FIND_ADDRESS:
             d = self.databyte & 0xfe
             # The READ/WRITE bit is only in address bytes, not data bytes.
             self.wr = (self.databyte & 1) and 1 or 0
-        elif self.state == self.FIND_DATA:
+        elif self.state == FIND_DATA:
             d = self.databyte
         else:
             # TODO: Error?
@@ -252,13 +259,13 @@ class Decoder():
         o = {'data': '0x%02x' % d}
 
         # TODO: Simplify.
-        if self.state == self.FIND_ADDRESS and self.wr == 1:
+        if self.state == FIND_ADDRESS and self.wr == 1:
             o['type'] = 'AW'
-        elif self.state == self.FIND_ADDRESS and self.wr == 0:
+        elif self.state == FIND_ADDRESS and self.wr == 0:
             o['type'] = 'AR'
-        elif self.state == self.FIND_DATA and self.wr == 1:
+        elif self.state == FIND_DATA and self.wr == 1:
             o['type'] = 'DW'
-        elif self.state == self.FIND_DATA and self.wr == 0:
+        elif self.state == FIND_DATA and self.wr == 0:
             o['type'] = 'DR'
 
         out.append(o)
@@ -270,9 +277,9 @@ class Decoder():
         self.bitcount = self.databyte = 0
         self.startsample = -1
 
-        if self.state == self.FIND_ADDRESS:
-            self.state = self.FIND_DATA
-        elif self.state == self.FIND_DATA:
+        if self.state == FIND_ADDRESS:
+            self.state = FIND_DATA
+        elif self.state == FIND_DATA:
             # There could be multiple data bytes in a row.
             # So, either find a STOP condition or another data byte next.
             pass
@@ -286,7 +293,7 @@ class Decoder():
         #      'data': None, 'ann': None},
         o = 'P'
         out.append(o)
-        self.state = self.FIND_START
+        self.state = FIND_START
         self.is_repeat_start = 0
         self.wr = -1
 
@@ -321,13 +328,13 @@ class Decoder():
             # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
 
             # State machine.
-            if self.state == self.FIND_START:
+            if self.state == FIND_START:
                 if self.is_start_condition(scl, sda):
                     out += self.find_start(scl, sda)
-            elif self.state == self.FIND_ADDRESS:
+            elif self.state == FIND_ADDRESS:
                 if self.is_data_bit(scl, sda):
                     out += self.find_address_or_data(scl, sda)
-            elif self.state == self.FIND_DATA:
+            elif self.state == FIND_DATA:
                 if self.is_data_bit(scl, sda):
                     out += self.find_address_or_data(scl, sda)
                 elif self.is_start_condition(scl, sda):
@@ -343,14 +350,5 @@ class Decoder():
             self.oldsda = sda
 
         if out != []:
-            sigrok.put(out)
-
-# Use psyco (if available) as it results in huge performance improvements.
-try:
-    import psyco
-    psyco.bind(decode)
-except ImportError:
-    pass
-
-import sigrok
+            self.put(out)