- out = []
- o = ack = d = ''
- bitcount = data = 0
- wr = startsample = -1
- IDLE, START, ADDRESS, DATA = range(4)
- state = IDLE
-
- # Get the channel/probe number of the SCL/SDA signals.
- scl_bit = metadata['signals']['scl']['ch']
- sda_bit = metadata['signals']['sda']['ch']
-
- # Get SCL/SDA bit values (0/1 for low/high) of the first sample.
- s = inbuf[0]
- oldscl = (s & (1 << scl_bit)) >> scl_bit
- oldsda = (s & (1 << sda_bit)) >> sda_bit
-
- # Loop over all samples.
- # TODO: Handle LAs with more/less than 8 channels.
- for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte...
- # Get SCL/SDA bit values (0/1 for low/high).
- scl = (s & (1 << scl_bit)) >> scl_bit
- sda = (s & (1 << sda_bit)) >> sda_bit
-
- # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
-
- # START condition (S): SDA = falling, SCL = high
- if (oldsda == 1 and sda == 0) and scl == 1:
- o = {'type': 'S', 'range': (samplenum, samplenum),
- 'data': None, 'ann': None},
- out.append(o)
- state = ADDRESS
- bitcount = data = 0
-
- # Data latching by transmitter: SCL = low
- elif (scl == 0):
- pass # TODO
-
- # Data sampling of receiver: SCL = rising
- elif (oldscl == 0 and scl == 1):
- if startsample == -1:
- startsample = samplenum
- bitcount += 1
-
- # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \
- # (samplenum, 8 - bitcount, sda))
-
- # Address and data are transmitted MSB-first.
- data <<= 1
- data |= sda
-
- if bitcount != 9:
+ # Address and data are transmitted MSB-first.
+ self.databyte <<= 1
+ self.databyte |= sda
+
+ # Return if we haven't collected all 8 + 1 bits, yet.
+ if self.bitcount != 9:
+ return []
+
+ # send raw output annotation before we start shifting out
+ # read/write and ack/nack bits
+ self.put(self.output_annotation, [ANN_RAW, ["0x%.2x" % self.databyte]])
+
+ # We received 8 address/data bits and the ACK/NACK bit.
+ self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
+
+ if self.state == FIND_ADDRESS:
+ d = self.databyte & 0xfe
+ # The READ/WRITE bit is only in address bytes, not data bytes.
+ self.wr = 1 if (self.databyte & 1) else 0
+ elif self.state == FIND_DATA:
+ d = self.databyte
+ else:
+ # TODO: Error?
+ pass
+
+ # last bit that came in was the ACK/NACK bit (1 = NACK)
+ if sda == 1:
+ ack_bit = 'NACK'
+ else:
+ ack_bit = 'ACK'
+
+ # TODO: Simplify.
+ if self.state == FIND_ADDRESS and self.wr == 1:
+ cmd = 'ADDRESS_WRITE'
+ elif self.state == FIND_ADDRESS and self.wr == 0:
+ cmd = 'ADDRESS_READ'
+ elif self.state == FIND_DATA and self.wr == 1:
+ cmd = 'DATA_WRITE'
+ elif self.state == FIND_DATA and self.wr == 0:
+ cmd = 'DATA_READ'
+ self.put(self.output_protocol, [ [cmd, d], [ack_bit] ] )
+ self.put(self.output_annotation, [ANN_SHIFTED, [
+ "%s" % protocol[cmd][0],
+ "0x%02x" % d,
+ "%s" % protocol[ack_bit][0]]
+ ] )
+ self.put(self.output_annotation, [ANN_SHIFTED_SHORT, [
+ "%s" % protocol[cmd][1],
+ "0x%02x" % d,
+ "%s" % protocol[ack_bit][1]]
+ ] )
+
+ self.bitcount = self.databyte = 0
+ self.startsample = -1
+
+ if self.state == FIND_ADDRESS:
+ self.state = FIND_DATA
+ elif self.state == FIND_DATA:
+ # There could be multiple data bytes in a row.
+ # So, either find a STOP condition or another data byte next.
+ pass
+
+ def found_stop(self, scl, sda):
+ self.put(self.output_protocol, [ 'STOP' ])
+ self.put(self.output_annotation, [ ANN_SHIFTED, [protocol['STOP'][0]] ])
+ self.put(self.output_annotation, [ ANN_SHIFTED_SHORT, [protocol['STOP'][1]] ])
+
+ self.state = FIND_START
+ self.is_repeat_start = 0
+ self.wr = -1
+
+ def put(self, output_id, data):
+ # inject sample range into the call up to sigrok
+ # TODO: 0-0 sample range for now
+ super(Decoder, self).put(0, 0, output_id, data)
+
+ def decode(self, timeoffset, duration, data):
+ for samplenum, (scl, sda) in data:
+ self.samplecnt += 1
+
+ # First sample: Save SCL/SDA value.
+ if self.oldscl == None:
+ self.oldscl = scl
+ self.oldsda = sda