##
## This file is part of the sigrok project.
##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
#
# START condition (S): SDA = falling, SCL = high
# Repeated START condition (Sr): same as S
+# Data bit sampling: SCL = rising
# STOP condition (P): SDA = rising, SCL = high
#
# All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
# TODO: Implement support for 7bit and 10bit slave addresses.
# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
# TODO: Implement support for detecting various bus errors.
-
-#
-# I2C output format:
-#
-# The output consists of a (Python) list of I2C "packets", each of which
-# has an (implicit) index number (its index in the list).
-# Each packet consists of a Python dict with certain key/value pairs.
-#
-# TODO: Make this a list later instead of a dict?
-#
-# 'type': (string)
-# - 'S' (START condition)
-# - 'Sr' (Repeated START)
-# - 'AR' (Address, read)
-# - 'AW' (Address, write)
-# - 'DR' (Data, read)
-# - 'DW' (Data, write)
-# - 'P' (STOP condition)
-# 'range': (tuple of 2 integers, the min/max samplenumber of this range)
-# - (min, max)
-# - min/max can also be identical.
-# 'data': (actual data as integer ???) TODO: This can be very variable...
-# 'ann': (string; additional annotations / comments)
-#
-# Example output:
-# [{'type': 'S', 'range': (150, 160), 'data': None, 'ann': 'Foobar'},
-# {'type': 'AW', 'range': (200, 300), 'data': 0x50, 'ann': 'Slave 4'},
-# {'type': 'DW', 'range': (310, 370), 'data': 0x00, 'ann': 'Init cmd'},
-# {'type': 'AR', 'range': (500, 560), 'data': 0x50, 'ann': 'Get stat'},
-# {'type': 'DR', 'range': (580, 640), 'data': 0xfe, 'ann': 'OK'},
-# {'type': 'P', 'range': (650, 660), 'data': None, 'ann': None}]
-#
-# Possible other events:
-# - Error event in case protocol looks broken:
-# [{'type': 'ERROR', 'range': (min, max),
-# 'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'},
-# [{'type': 'ERROR', 'range': (min, max),
-# 'data': TODO, 'ann': 'TODO'},
-# - TODO: Make list of possible errors accessible as metadata?
-#
# TODO: I2C address of slaves.
# TODO: Handle multiple different I2C devices on same bus
# -> we need to decode multiple protocols at the same time.
-# TODO: range: Always contiguous? Splitted ranges? Multiple per event?
-#
#
-# I2C input format:
+# I2C protocol output format:
+#
+# The protocol output consists of a (Python) list of I2C "packets", each of
+# which is of the form
+#
+# [<i2c_command>, <data>, <ack_bit>]
#
-# signals:
-# [[id, channel, description], ...] # TODO
+# <i2c_command> is one of:
+# - 'START' (START condition)
+# - 'START_REPEAT' (Repeated START)
+# - 'ADDRESS_READ' (Slave address, read)
+# - 'ADDRESS_WRITE' (Slave address, write)
+# - 'DATA_READ' (Data, read)
+# - 'DATA_WRITE' (Data, write)
+# - 'STOP' (STOP condition)
#
-# Example:
-# {'id': 'SCL', 'ch': 5, 'desc': 'Serial clock line'}
-# {'id': 'SDA', 'ch': 7, 'desc': 'Serial data line'}
-# ...
+# <data> is the data or address byte associated with the ADDRESS_* and DATA_*
+# command. For START, START_REPEAT and STOP, this is None.
#
-# {'inbuf': [...],
-# 'signals': [{'SCL': }]}
+# <ack_bit> is either 'ACK' or 'NACK', but may also be None.
#
-def decode(l):
- print(l)
- sigrok.put(l)
-
-
-
-def decode2(inbuf):
- """I2C protocol decoder"""
-
- # FIXME: Get the data in the correct format in the first place.
- inbuf = [ord(x) for x in inbuf]
-
- # FIXME: This should be passed in as metadata, not hardcoded here.
- metadata = {
- 'numchannels': 8,
- 'signals': {
- 'scl': {'ch': 5, 'name': 'SCL', 'desc': 'Serial clock line'},
- 'sda': {'ch': 7, 'name': 'SDA', 'desc': 'Serial data line'},
- },
- }
-
- out = []
- o = ack = d = ''
- bitcount = data = 0
- wr = startsample = -1
- IDLE, START, ADDRESS, DATA = range(4)
- state = IDLE
-
- # Get the channel/probe number of the SCL/SDA signals.
- scl_bit = metadata['signals']['scl']['ch']
- sda_bit = metadata['signals']['sda']['ch']
-
- # Get SCL/SDA bit values (0/1 for low/high) of the first sample.
- s = inbuf[0]
- oldscl = (s & (1 << scl_bit)) >> scl_bit
- oldsda = (s & (1 << sda_bit)) >> sda_bit
-
- # Loop over all samples.
- # TODO: Handle LAs with more/less than 8 channels.
- for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte...
- # Get SCL/SDA bit values (0/1 for low/high).
- scl = (s & (1 << scl_bit)) >> scl_bit
- sda = (s & (1 << sda_bit)) >> sda_bit
-
- # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
-
- # START condition (S): SDA = falling, SCL = high
- if (oldsda == 1 and sda == 0) and scl == 1:
- o = {'type': 'S', 'range': (samplenum, samplenum),
- 'data': None, 'ann': None},
- out.append(o)
- state = ADDRESS
- bitcount = data = 0
-
- # Data latching by transmitter: SCL = low
- elif (scl == 0):
- pass # TODO
-
- # Data sampling of receiver: SCL = rising
- elif (oldscl == 0 and scl == 1):
- if startsample == -1:
- startsample = samplenum
- bitcount += 1
-
- # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \
- # (samplenum, 8 - bitcount, sda))
-
- # Address and data are transmitted MSB-first.
- data <<= 1
- data |= sda
-
- if bitcount != 9:
- continue
-
- # We received 8 address/data bits and the ACK/NACK bit.
- data >>= 1 # Shift out unwanted ACK/NACK bit here.
- ack = (sda == 1) and 'N' or 'A'
- d = (state == ADDRESS) and (data & 0xfe) or data
- if state == ADDRESS:
- wr = (data & 1) and 1 or 0
- state = DATA
- o = {'type': state,
- 'range': (startsample, samplenum - 1),
- 'data': d, 'ann': None}
- if state == ADDRESS and wr == 1:
- o['type'] = 'AW'
- elif state == ADDRESS and wr == 0:
- o['type'] = 'AR'
- elif state == DATA and wr == 1:
- o['type'] = 'DW'
- elif state == DATA and wr == 0:
- o['type'] = 'DR'
- out.append(o)
- o = {'type': ack, 'range': (samplenum, samplenum),
- 'data': None, 'ann': None}
- out.append(o)
- bitcount = data = startsample = 0
- startsample = -1
-
- # STOP condition (P): SDA = rising, SCL = high
- elif (oldsda == 0 and sda == 1) and scl == 1:
- o = {'type': 'P', 'range': (samplenum, samplenum),
- 'data': None, 'ann': None},
- out.append(o)
- state = IDLE
- wr = -1
-
- # Save current SDA/SCL values for the next round.
- oldscl = scl
- oldsda = sda
-
- # FIXME: Just for testing...
- return str(out)
-
-register = {
- 'id': 'i2c',
- 'name': 'I2C',
- 'longname': 'Inter-Integrated Circuit (I2C) bus',
- 'desc': 'I2C is a two-wire, multi-master, serial bus.',
- 'longdesc': '...',
- 'author': 'Uwe Hermann',
- 'email': 'uwe@hermann-uwe.de',
- 'license': 'gplv2+',
- 'in': ['logic'],
- 'out': ['i2c'],
- 'probes': [
- ['scl', 'Serial clock line'],
- ['sda', 'Serial data line'],
- ],
- 'options': {
- 'address-space': ['Address space (in bits)', 7],
- },
- # 'start': start,
- # 'report': report,
+import sigrokdecode as srd
+
+# Annotation feed formats
+ANN_SHIFTED = 0
+ANN_SHIFTED_SHORT = 1
+ANN_RAW = 2
+
+# Values are verbose and short annotation, respectively.
+protocol = {
+ 'START': ['START', 'S'],
+ 'START_REPEAT': ['START REPEAT', 'Sr'],
+ 'STOP': ['STOP', 'P'],
+ 'ACK': ['ACK', 'A'],
+ 'NACK': ['NACK', 'N'],
+ 'ADDRESS_READ': ['ADDRESS READ', 'AR'],
+ 'ADDRESS_WRITE': ['ADDRESS WRITE', 'AW'],
+ 'DATA_READ': ['DATA READ', 'DR'],
+ 'DATA_WRITE': ['DATA WRITE', 'DW'],
}
-# Use psyco (if available) as it results in huge performance improvements.
-try:
- import psyco
- psyco.bind(decode)
-except ImportError:
- pass
+# States
+FIND_START = 0
+FIND_ADDRESS = 1
+FIND_DATA = 2
+
+class Decoder(srd.Decoder):
+ id = 'i2c'
+ name = 'I2C'
+ longname = 'Inter-Integrated Circuit (I2C) bus'
+ desc = 'I2C is a two-wire, multi-master, serial bus.'
+ longdesc = '...'
+ author = 'Uwe Hermann'
+ email = 'uwe@hermann-uwe.de'
+ license = 'gplv2+'
+ inputs = ['logic']
+ outputs = ['i2c']
+ probes = [
+ {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
+ {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
+ ]
+ options = {
+ 'address-space': ['Address space (in bits)', 7],
+ }
+ annotations = [
+ # ANN_SHIFTED
+ ['7-bit shifted hex',
+ 'Read/write bit shifted out from the 8-bit I2C slave address'],
+ # ANN_SHIFTED_SHORT
+ ['7-bit shifted hex (short)',
+ 'Read/write bit shifted out from the 8-bit I2C slave address'],
+ # ANN_RAW
+ ['Raw hex', 'Unaltered raw data'],
+ ]
+
+ def __init__(self, **kwargs):
+ self.samplecnt = 0
+ self.bitcount = 0
+ self.databyte = 0
+ self.wr = -1
+ self.startsample = -1
+ self.is_repeat_start = 0
+ self.state = FIND_START
+ self.oldscl = None
+ self.oldsda = None
+
+ def start(self, metadata):
+ self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
+ self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
+
+ def report(self):
+ pass
+
+ def is_start_condition(self, scl, sda):
+ # START condition (S): SDA = falling, SCL = high
+ if (self.oldsda == 1 and sda == 0) and scl == 1:
+ return True
+ return False
+
+ def is_data_bit(self, scl, sda):
+ # Data sampling of receiver: SCL = rising
+ if self.oldscl == 0 and scl == 1:
+ return True
+ return False
+
+ def is_stop_condition(self, scl, sda):
+ # STOP condition (P): SDA = rising, SCL = high
+ if (self.oldsda == 0 and sda == 1) and scl == 1:
+ return True
+ return False
+
+ def found_start(self, scl, sda):
+ cmd = 'START_REPEAT' if (self.is_repeat_start == 1) else 'START'
+
+ self.put(self.out_proto, [cmd, None, None])
+ self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
+ self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])
+
+ self.state = FIND_ADDRESS
+ self.bitcount = self.databyte = 0
+ self.is_repeat_start = 1
+ self.wr = -1
+
+ def found_address_or_data(self, scl, sda):
+ # Gather 8 bits of data plus the ACK/NACK bit.
+
+ if self.startsample == -1:
+ # TODO: Should be samplenum, as received from the feed.
+ self.startsample = self.samplecnt
+ self.bitcount += 1
+
+ # Address and data are transmitted MSB-first.
+ self.databyte <<= 1
+ self.databyte |= sda
+
+ # Return if we haven't collected all 8 + 1 bits, yet.
+ if self.bitcount != 9:
+ return
+
+ # Send raw output annotation before we start shifting out
+ # read/write and ack/nack bits.
+ self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
+
+ # We received 8 address/data bits and the ACK/NACK bit.
+ self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
+
+ if self.state == FIND_ADDRESS:
+ # The READ/WRITE bit is only in address bytes, not data bytes.
+ self.wr = 0 if (self.databyte & 1) else 1
+ d = self.databyte >> 1
+ elif self.state == FIND_DATA:
+ d = self.databyte
+ else:
+ # TODO: Error?
+ pass
+
+ # Last bit that came in was the ACK/NACK bit (1 = NACK).
+ ack_bit = 'NACK' if (sda == 1) else 'ACK'
+
+ if self.state == FIND_ADDRESS and self.wr == 1:
+ cmd = 'ADDRESS_WRITE'
+ elif self.state == FIND_ADDRESS and self.wr == 0:
+ cmd = 'ADDRESS_READ'
+ elif self.state == FIND_DATA and self.wr == 1:
+ cmd = 'DATA_WRITE'
+ elif self.state == FIND_DATA and self.wr == 0:
+ cmd = 'DATA_READ'
+
+ self.put(self.out_proto, [cmd, d, ack_bit])
+ self.put(self.out_ann, [ANN_SHIFTED, [
+ '%s' % protocol[cmd][0],
+ '0x%02x' % d,
+ '%s' % protocol[ack_bit][0]]
+ ])
+ self.put(self.out_ann, [ANN_SHIFTED_SHORT, [
+ '%s' % protocol[cmd][1],
+ '0x%02x' % d,
+ '%s' % protocol[ack_bit][1]]
+ ])
+
+ self.bitcount = self.databyte = 0
+ self.startsample = -1
+
+ if self.state == FIND_ADDRESS:
+ self.state = FIND_DATA
+ elif self.state == FIND_DATA:
+ # There could be multiple data bytes in a row.
+ # So, either find a STOP condition or another data byte next.
+ pass
+
+ def found_stop(self, scl, sda):
+ self.put(self.out_proto, ['STOP', None, None])
+ self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
+ self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])
+
+ self.state = FIND_START
+ self.is_repeat_start = 0
+ self.wr = -1
+
+ def put(self, output_id, data):
+ # Inject sample range into the call up to sigrok.
+ # TODO: 0-0 sample range for now.
+ super(Decoder, self).put(0, 0, output_id, data)
+
+ def decode(self, timeoffset, duration, data):
+ for samplenum, (scl, sda) in data:
+ self.samplecnt += 1
+
+ # First sample: Save SCL/SDA value.
+ if self.oldscl == None:
+ self.oldscl = scl
+ self.oldsda = sda
+ continue
+
+ # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
+
+ # State machine.
+ if self.state == FIND_START:
+ if self.is_start_condition(scl, sda):
+ self.found_start(scl, sda)
+ elif self.state == FIND_ADDRESS:
+ if self.is_data_bit(scl, sda):
+ self.found_address_or_data(scl, sda)
+ elif self.state == FIND_DATA:
+ if self.is_data_bit(scl, sda):
+ self.found_address_or_data(scl, sda)
+ elif self.is_start_condition(scl, sda):
+ self.found_start(scl, sda)
+ elif self.is_stop_condition(scl, sda):
+ self.found_stop(scl, sda)
+ else:
+ # TODO: Error?
+ pass
+
+ # Save current SDA/SCL values for the next round.
+ self.oldscl = scl
+ self.oldsda = sda
projects / libsigrokdecode.git / blobdiff