'Hours', 'Day', 'Date', 'Month', 'Year', 'OUT', 'SQWE', 'RS', 'RAM',
)
+rates = {
+ 0b00: '1Hz',
+ 0b01: '4096kHz',
+ 0b10: '8192kHz',
+ 0b11: '32768kHz',
+}
+
def regs_and_bits():
l = [('reg-' + r.lower(), r + ' register') for r in regs]
l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits]
self.putd(7, 0, [19, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
def handle_reg_0x07(self, b): # Control Register
- pass
+ self.putd(7, 0, [7, ['Control', 'Ctrl', 'C']])
+ for i in (6, 5, 3, 2):
+ self.putr(i)
+ o = 1 if (b & (1 << 7)) else 0
+ s = 1 if (b & (1 << 4)) else 0
+ s2 = 'en' if (b & (1 << 4)) else 'dis'
+ r = rates[b & 0x03]
+ self.putd(7, 7, [20, ['Output control: %d' % o,
+ 'OUT: %d' % o, 'O: %d' % o, 'O']])
+ self.putd(4, 4, [21, ['Square wave output: %sabled' % s2,
+ 'SQWE: %sabled' % s2, 'SQWE: %d' % s, 'S: %d' % s, 'S']])
+ self.putd(1, 0, [22, ['Square wave output rate: %s' % r,
+ 'Square wave rate: %s' % r, 'SQW rate: %s' % r, 'Rate: %s' % r,
+ 'RS: %s' % s, 'RS', 'R']])
+
+ def handle_reg_0x3f(self, b): # RAM (bytes 0x08-0x3f)
+ self.putd(7, 0, [8, ['RAM', 'R']])
+ self.putd(7, 0, [23, ['SRAM: 0x%02X' % b, '0x%02X' % b]])
+
+ def output_datetime(self, cls, rw):
+ # TODO: Handle read/write of only parts of these items.
+ d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
+ days_of_week[self.days - 1], self.date, self.months,
+ self.years, self.hours, self.minutes, self.seconds)
+ self.put(self.block_start_sample, self.es, self.out_ann,
+ [cls, ['%s date/time: %s' % (rw, d)]])
+
+ def handle_reg(self, b):
+ r = self.reg if self.reg < 8 else 0x3f
+ fn = getattr(self, 'handle_reg_0x%02x' % r)
+ fn(b)
+ self.reg += 1
def decode(self, ss, es, data):
cmd, databyte = data
self.reg = databyte
self.state = 'WRITE RTC REGS'
elif self.state == 'WRITE RTC REGS':
- # If we see a Repeated Start here, it's probably an RTC read.
+ # If we see a Repeated Start here, it's an RTC read.
if cmd == 'START REPEAT':
self.state = 'READ RTC REGS'
return
# Otherwise: Get data bytes until a STOP condition occurs.
if cmd == 'DATA WRITE':
- handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
- handle_reg(databyte)
- self.reg += 1
- # TODO: Check for NACK!
+ self.handle_reg(databyte)
elif cmd == 'STOP':
- # TODO: Handle read/write of only parts of these items.
- d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
- days_of_week[self.days - 1], self.date, self.months,
- self.years, self.hours, self.minutes, self.seconds)
- self.put(self.block_start_sample, es, self.out_ann,
- [25, ['Written date/time: %s' % d]])
+ self.output_datetime(25, 'Written')
self.state = 'IDLE'
- else:
- pass # TODO
elif self.state == 'READ RTC REGS':
# Wait for an address read operation.
# TODO: We should only handle packets to the RTC slave (0x68).
if cmd == 'ADDRESS READ':
self.state = 'READ RTC REGS2'
return
- else:
- pass # TODO
elif self.state == 'READ RTC REGS2':
if cmd == 'DATA READ':
- handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
- handle_reg(databyte)
- self.reg += 1
- # TODO: Check for NACK!
+ self.handle_reg(databyte)
elif cmd == 'STOP':
- d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
- days_of_week[self.days - 1], self.date, self.months,
- self.years, self.hours, self.minutes, self.seconds)
- self.put(self.block_start_sample, es, self.out_ann,
- [24, ['Read date/time: %s' % d]])
+ self.output_datetime(24, 'Read')
self.state = 'IDLE'
- else:
- pass # TODO?