ds1307: Warn about (and ignore) non-DS1307 traffic.

[libsigrokdecode.git] / decoders / ds1307 / pd.py

diff --git a/decoders/ds1307/pd.py b/decoders/ds1307/pd.py
index d718c93fa7993804d9a76a347e38dfbc7343c082..800f7a0b2ebe4a6d602f3d05e5126ae84b2c511b 100644 (file)
--- a/decoders/ds1307/pd.py
+++ b/decoders/ds1307/pd.py
@@ -44,6 +44,8 @@ rates = {
     0b11: '32768kHz',
 }
 
+DS1307_I2C_ADDRESS = 0x68
+
 def regs_and_bits():
     l = [('reg-' + r.lower(), r + ' register') for r in regs]
     l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits]
@@ -67,11 +69,13 @@ class Decoder(srd.Decoder):
         ('write-datetime', 'Write date/time'),
         ('reg-read', 'Register read'),
         ('reg-write', 'Register write'),
+        ('warnings', 'Warnings'),
     )
     annotation_rows = (
         ('bits', 'Bits', tuple(range(9, 24))),
         ('regs', 'Registers', tuple(range(9))),
         ('date-time', 'Date/time', (24, 25, 26, 27)),
+        ('warnings', 'Warnings', (28,)),
     )
 
     def __init__(self, **kwargs):
@@ -171,6 +175,35 @@ class Decoder(srd.Decoder):
             'Square wave rate: %s' % r, 'SQW rate: %s' % r, 'Rate: %s' % r,
             'RS: %s' % s, 'RS', 'R']])
 
+    def handle_reg_0x3f(self, b): # RAM (bytes 0x08-0x3f)
+        self.putd(7, 0, [8, ['RAM', 'R']])
+        self.putd(7, 0, [23, ['SRAM: 0x%02X' % b, '0x%02X' % b]])
+
+    def output_datetime(self, cls, rw):
+        # TODO: Handle read/write of only parts of these items.
+        d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
+            days_of_week[self.days - 1], self.date, self.months,
+            self.years, self.hours, self.minutes, self.seconds)
+        self.put(self.block_start_sample, self.es, self.out_ann,
+                 [cls, ['%s date/time: %s' % (rw, d)]])
+
+    def handle_reg(self, b):
+        r = self.reg if self.reg < 8 else 0x3f
+        fn = getattr(self, 'handle_reg_0x%02x' % r)
+        fn(b)
+        # Honor address auto-increment feature of the DS1307. When the
+        # address reaches 0x3f, it will wrap around to address 0.
+        self.reg += 1
+        if self.reg > 0x3f:
+            self.reg = 0
+
+    def is_correct_chip(self, addr):
+        if addr == DS1307_I2C_ADDRESS:
+            return True
+        self.put(self.block_start_sample, self.es, self.out_ann,
+                 [28, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]])
+        return False
+
     def decode(self, ss, es, data):
         cmd, databyte = data
 
@@ -192,9 +225,11 @@ class Decoder(srd.Decoder):
             self.block_start_sample = ss
         elif self.state == 'GET SLAVE ADDR':
             # Wait for an address write operation.
-            # TODO: We should only handle packets to the RTC slave (0x68).
             if cmd != 'ADDRESS WRITE':
                 return
+            if not self.is_correct_chip(databyte):
+                self.state = 'IDLE'
+                return
             self.state = 'GET REG ADDR'
         elif self.state == 'GET REG ADDR':
             # Wait for a data write (master selects the slave register).
@@ -203,46 +238,27 @@ class Decoder(srd.Decoder):
             self.reg = databyte
             self.state = 'WRITE RTC REGS'
         elif self.state == 'WRITE RTC REGS':
-            # If we see a Repeated Start here, it's probably an RTC read.
+            # If we see a Repeated Start here, it's an RTC read.
             if cmd == 'START REPEAT':
                 self.state = 'READ RTC REGS'
                 return
             # Otherwise: Get data bytes until a STOP condition occurs.
             if cmd == 'DATA WRITE':
-                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
-                handle_reg(databyte)
-                self.reg += 1
-                # TODO: Check for NACK!
+                self.handle_reg(databyte)
             elif cmd == 'STOP':
-                # TODO: Handle read/write of only parts of these items.
-                d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
-                    days_of_week[self.days - 1], self.date, self.months,
-                    self.years, self.hours, self.minutes, self.seconds)
-                self.put(self.block_start_sample, es, self.out_ann,
-                         [25, ['Written date/time: %s' % d]])
+                self.output_datetime(25, 'Written')
                 self.state = 'IDLE'
-            else:
-                pass # TODO
         elif self.state == 'READ RTC REGS':
             # Wait for an address read operation.
-            # TODO: We should only handle packets to the RTC slave (0x68).
-            if cmd == 'ADDRESS READ':
-                self.state = 'READ RTC REGS2'
+            if cmd != 'ADDRESS READ':
+                return
+            if not self.is_correct_chip(databyte):
+                self.state = 'IDLE'
                 return
-            else:
-                pass # TODO
+            self.state = 'READ RTC REGS2'
         elif self.state == 'READ RTC REGS2':
             if cmd == 'DATA READ':
-                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
-                handle_reg(databyte)
-                self.reg += 1
-                # TODO: Check for NACK!
+                self.handle_reg(databyte)
             elif cmd == 'STOP':
-                d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
-                    days_of_week[self.days - 1], self.date, self.months,
-                    self.years, self.hours, self.minutes, self.seconds)
-                self.put(self.block_start_sample, es, self.out_ann,
-                         [24, ['Read date/time: %s' % d]])
+                self.output_datetime(24, 'Read')
                 self.state = 'IDLE'
-            else:
-                pass # TODO?