license: remove FSF postal address from boiler plate license text

[libsigrokdecode.git] / decoders / dcf77 / pd.py

diff --git a/decoders/dcf77/pd.py b/decoders/dcf77/pd.py
index 7cc85f62f8c267c7fb4f70fe54a564122b407eb9..b643631081b7e1babed940146b8f87f5aa0136bb 100644 (file)
--- a/decoders/dcf77/pd.py
+++ b/decoders/dcf77/pd.py
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the libsigrokdecode project.
 ##
-## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2012-2016 Uwe Hermann <uwe@hermann-uwe.de>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -14,19 +14,18 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
 import calendar
+from common.srdhelper import bcd2int
 
-# Return the specified BCD number (max. 8 bits) as integer.
-def bcd2int(b):
-    return (b & 0x0f) + ((b >> 4) * 10)
+class SamplerateError(Exception):
+    pass
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 3
     id = 'dcf77'
     name = 'DCF77'
     longname = 'DCF77 time protocol'
@@ -34,7 +33,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['dcf77']
-    probes = (
+    channels = (
         {'id': 'data', 'name': 'DATA', 'desc': 'DATA line'},
     )
     annotations = (
@@ -65,21 +64,20 @@ class Decoder(srd.Decoder):
         ('warnings', 'Warnings', (19,)),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         self.samplerate = None
         self.state = 'WAIT FOR RISING EDGE'
-        self.oldpins = None
-        self.oldval = None
-        self.samplenum = 0
         self.ss_bit = self.ss_bit_old = self.es_bit = self.ss_block = 0
         self.datebits = []
         self.bitcount = 0 # Counter for the DCF77 bits (0..58)
         self.dcf77_bitnumber_is_known = 0
 
     def start(self):
-        # self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
+        # Assume that the initial pin state is logic 1.
+        self.initial_pins = [1]
+
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
             self.samplerate = value
@@ -240,26 +238,18 @@ class Decoder(srd.Decoder):
             # Even parity over date bits (36-58): DCF77 bit 58.
             parity = self.datebits.count(1)
             s = 'OK' if ((parity % 2) == 0) else 'INVALID!'
-            self.putx([16, ['Date parity: %s' % s, 'DP: %s' %s]])
+            self.putx([16, ['Date parity: %s' % s, 'DP: %s' % s]])
             self.datebits = []
         else:
             raise Exception('Invalid DCF77 bit: %d' % c)
 
-    def decode(self, ss, es, data):
-        if self.samplerate is None:
-            raise Exception("Cannot decode without samplerate.")
-        for (self.samplenum, pins) in data:
-
-            # Ignore identical samples early on (for performance reasons).
-            if self.oldpins == pins:
-                continue
-            self.oldpins, (val,) = pins, pins
-
+    def decode(self):
+        if not self.samplerate:
+            raise SamplerateError('Cannot decode without samplerate.')
+        while True:
             if self.state == 'WAIT FOR RISING EDGE':
                 # Wait until the next rising edge occurs.
-                if not (self.oldval == 0 and val == 1):
-                    self.oldval = val
-                    continue
+                self.wait({0: 'r'})
 
                 # Save the sample number where the DCF77 bit begins.
                 self.ss_bit = self.samplenum
@@ -284,9 +274,7 @@ class Decoder(srd.Decoder):
 
             elif self.state == 'GET BIT':
                 # Wait until the next falling edge occurs.
-                if not (self.oldval == 1 and val == 0):
-                    self.oldval = val
-                    continue
+                self.wait({0: 'f'})
 
                 # Save the sample number where the DCF77 bit ends.
                 self.es_bit = self.samplenum
@@ -310,9 +298,3 @@ class Decoder(srd.Decoder):
                     self.bitcount += 1
 
                 self.state = 'WAIT FOR RISING EDGE'
-
-            else:
-                raise Exception('Invalid state: %s' % self.state)
-
-            self.oldval = val
-