2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
21 from common.srdhelper import bitpack
22 from math import floor, ceil
28 [<ptype>, <rxtx>, <pdata>]
30 This is the list of <ptype>s and their respective <pdata> values:
31 - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
32 - 'DATA': This is always a tuple containing two items:
33 - 1st item: the (integer) value of the UART data. Valid values
34 range from 0 to 511 (as the data can be up to 9 bits in size).
35 - 2nd item: the list of individual data bits and their ss/es numbers.
36 - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
37 - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
38 - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
39 - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
40 - 'PARITY ERROR': The data is a tuple with two entries. The first one is
41 the expected parity value, the second is the actual parity value.
42 - 'BREAK': The data is always 0.
43 - 'FRAME': The data is always a tuple containing two items: The (integer)
44 value of the UART data, and a boolean which reflects the validity of the
46 - 'IDLE': The data is always 0.
48 The <rxtx> field is 0 for RX packets, 1 for TX packets.
51 # Used for differentiating between the two data directions.
55 # Given a parity type to check (odd, even, zero, one), the value of the
56 # parity bit, the value of the data, and the length of the data (5-9 bits,
57 # usually 8 bits) return True if the parity is correct, False otherwise.
58 # 'none' is _not_ allowed as value for 'parity_type'.
59 def parity_ok(parity_type, parity_bit, data, data_bits):
61 if parity_type == 'ignore':
64 # Handle easy cases first (parity bit is always 1 or 0).
65 if parity_type == 'zero':
66 return parity_bit == 0
67 elif parity_type == 'one':
68 return parity_bit == 1
70 # Count number of 1 (high) bits in the data (and the parity bit itself!).
71 ones = bin(data).count('1') + parity_bit
73 # Check for odd/even parity.
74 if parity_type == 'odd':
75 return (ones % 2) == 1
76 elif parity_type == 'even':
77 return (ones % 2) == 0
79 class SamplerateError(Exception):
82 class ChannelError(Exception):
85 class Decoder(srd.Decoder):
89 longname = 'Universal Asynchronous Receiver/Transmitter'
90 desc = 'Asynchronous, serial bus.'
94 tags = ['Embedded/industrial']
96 # Allow specifying only one of the signals, e.g. if only one data
97 # direction exists (or is relevant).
98 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
99 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
102 {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
103 {'id': 'data_bits', 'desc': 'Data bits', 'default': 8,
104 'values': (5, 6, 7, 8, 9)},
105 {'id': 'parity', 'desc': 'Parity', 'default': 'none',
106 'values': ('none', 'odd', 'even', 'zero', 'one', 'ignore')},
107 {'id': 'stop_bits', 'desc': 'Stop bits', 'default': 1.0,
108 'values': (0.0, 0.5, 1.0, 1.5)},
109 {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
110 'values': ('lsb-first', 'msb-first')},
111 {'id': 'format', 'desc': 'Data format', 'default': 'hex',
112 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
113 {'id': 'invert_rx', 'desc': 'Invert RX', 'default': 'no',
114 'values': ('yes', 'no')},
115 {'id': 'invert_tx', 'desc': 'Invert TX', 'default': 'no',
116 'values': ('yes', 'no')},
117 {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 50},
118 {'id': 'rx_packet_delim', 'desc': 'RX packet delimiter (decimal)',
120 {'id': 'tx_packet_delim', 'desc': 'TX packet delimiter (decimal)',
122 {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1},
123 {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1},
126 ('rx-data', 'RX data'),
127 ('tx-data', 'TX data'),
128 ('rx-start', 'RX start bits'),
129 ('tx-start', 'TX start bits'),
130 ('rx-parity-ok', 'RX parity OK bits'),
131 ('tx-parity-ok', 'TX parity OK bits'),
132 ('rx-parity-err', 'RX parity error bits'),
133 ('tx-parity-err', 'TX parity error bits'),
134 ('rx-stop', 'RX stop bits'),
135 ('tx-stop', 'TX stop bits'),
136 ('rx-warnings', 'RX warnings'),
137 ('tx-warnings', 'TX warnings'),
138 ('rx-data-bits', 'RX data bits'),
139 ('tx-data-bits', 'TX data bits'),
140 ('rx-break', 'RX break'),
141 ('tx-break', 'TX break'),
142 ('rx-packet', 'RX packet'),
143 ('tx-packet', 'TX packet'),
146 ('rx-data-bits', 'RX bits', (12,)),
147 ('rx-data', 'RX', (0, 2, 4, 6, 8)),
148 ('rx-warnings', 'RX warnings', (10,)),
149 ('rx-break', 'RX break', (14,)),
150 ('rx-packets', 'RX packets', (16,)),
151 ('tx-data-bits', 'TX bits', (13,)),
152 ('tx-data', 'TX', (1, 3, 5, 7, 9)),
153 ('tx-warnings', 'TX warnings', (11,)),
154 ('tx-break', 'TX break', (15,)),
155 ('tx-packets', 'TX packets', (17,)),
160 ('rxtx', 'RX/TX dump'),
162 idle_state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
164 def putx(self, rxtx, data):
165 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
166 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
168 def putx_packet(self, rxtx, data):
169 s, halfbit = self.ss_packet[rxtx], self.bit_width / 2.0
170 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
172 def putpx(self, rxtx, data):
173 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
174 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data)
176 def putg(self, data):
177 s, halfbit = self.samplenum, self.bit_width / 2.0
178 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_ann, data)
180 def putp(self, data):
181 s, halfbit = self.samplenum, self.bit_width / 2.0
182 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data)
184 def putgse(self, ss, es, data):
185 self.put(ss, es, self.out_ann, data)
187 def putpse(self, ss, es, data):
188 self.put(ss, es, self.out_python, data)
190 def putbin(self, rxtx, data):
191 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
192 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
198 self.samplerate = None
199 self.frame_start = [-1, -1]
200 self.frame_valid = [None, None]
201 self.startbit = [-1, -1]
202 self.cur_data_bit = [0, 0]
203 self.datavalue = [0, 0]
204 self.paritybit = [-1, -1]
205 self.stopbit1 = [-1, -1]
206 self.startsample = [-1, -1]
207 self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
208 self.databits = [[], []]
209 self.break_start = [None, None]
210 self.packet_cache = [[], []]
211 self.ss_packet, self.es_packet = [None, None], [None, None]
212 self.idle_start = [None, None]
215 self.out_python = self.register(srd.OUTPUT_PYTHON)
216 self.out_binary = self.register(srd.OUTPUT_BINARY)
217 self.out_ann = self.register(srd.OUTPUT_ANN)
218 self.bw = (self.options['data_bits'] + 7) // 8
220 def metadata(self, key, value):
221 if key == srd.SRD_CONF_SAMPLERATE:
222 self.samplerate = value
223 # The width of one UART bit in number of samples.
224 self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
226 def get_sample_point(self, rxtx, bitnum):
227 # Determine absolute sample number of a bit slot's sample point.
228 # Counts for UART bits start from 0 (0 = start bit, 1..x = data,
229 # x+1 = parity bit (if used) or the first stop bit, and so on).
230 # Accept a position in the range of 1-99% of the full bit width.
231 # Assume 50% for invalid input specs for backwards compatibility.
232 perc = self.options['sample_point'] or 50
233 if not perc or perc not in range(1, 100):
236 bitpos = (self.bit_width - 1) * perc
237 bitpos += self.frame_start[rxtx]
238 bitpos += bitnum * self.bit_width
241 def wait_for_start_bit(self, rxtx, signal):
242 # Save the sample number where the start bit begins.
243 self.frame_start[rxtx] = self.samplenum
244 self.frame_valid[rxtx] = True
246 self.state[rxtx] = 'GET START BIT'
248 def get_start_bit(self, rxtx, signal):
249 self.startbit[rxtx] = signal
251 # The startbit must be 0. If not, we report an error and wait
252 # for the next start bit (assuming this one was spurious).
253 if self.startbit[rxtx] != 0:
254 self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
255 self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
256 self.frame_valid[rxtx] = False
257 es = self.samplenum + ceil(self.bit_width / 2.0)
258 self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
259 (self.datavalue[rxtx], self.frame_valid[rxtx])])
260 self.state[rxtx] = 'WAIT FOR START BIT'
263 self.cur_data_bit[rxtx] = 0
264 self.datavalue[rxtx] = 0
265 self.startsample[rxtx] = -1
267 self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
268 self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
270 self.state[rxtx] = 'GET DATA BITS'
272 def handle_packet(self, rxtx):
273 d = 'rx' if (rxtx == RX) else 'tx'
274 delim = self.options[d + '_packet_delim']
275 plen = self.options[d + '_packet_len']
276 if delim == -1 and plen == -1:
279 # Cache data values until we see the delimiter and/or the specified
280 # packet length has been reached (whichever happens first).
281 if len(self.packet_cache[rxtx]) == 0:
282 self.ss_packet[rxtx] = self.startsample[rxtx]
283 self.packet_cache[rxtx].append(self.datavalue[rxtx])
284 if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen:
285 self.es_packet[rxtx] = self.samplenum
287 for b in self.packet_cache[rxtx]:
288 s += self.format_value(b)
289 if self.options['format'] != 'ascii':
291 if self.options['format'] != 'ascii' and s[-1] == ' ':
292 s = s[:-1] # Drop trailing space.
293 self.putx_packet(rxtx, [16 + rxtx, [s]])
294 self.packet_cache[rxtx] = []
296 def get_data_bits(self, rxtx, signal):
297 # Save the sample number of the middle of the first data bit.
298 if self.startsample[rxtx] == -1:
299 self.startsample[rxtx] = self.samplenum
301 self.putg([rxtx + 12, ['%d' % signal]])
303 # Store individual data bits and their start/end samplenumbers.
304 s, halfbit = self.samplenum, int(self.bit_width / 2)
305 self.databits[rxtx].append([signal, s - halfbit, s + halfbit])
307 # Return here, unless we already received all data bits.
308 self.cur_data_bit[rxtx] += 1
309 if self.cur_data_bit[rxtx] < self.options['data_bits']:
312 # Convert accumulated data bits to a data value.
313 bits = [b[0] for b in self.databits[rxtx]]
314 if self.options['bit_order'] == 'msb-first':
316 self.datavalue[rxtx] = bitpack(bits)
317 self.putpx(rxtx, ['DATA', rxtx,
318 (self.datavalue[rxtx], self.databits[rxtx])])
320 b = self.datavalue[rxtx]
321 formatted = self.format_value(b)
322 if formatted is not None:
323 self.putx(rxtx, [rxtx, [formatted]])
325 bdata = b.to_bytes(self.bw, byteorder='big')
326 self.putbin(rxtx, [rxtx, bdata])
327 self.putbin(rxtx, [2, bdata])
329 self.handle_packet(rxtx)
331 self.databits[rxtx] = []
333 # Advance to either reception of the parity bit, or reception of
334 # the STOP bits if parity is not applicable.
335 self.state[rxtx] = 'GET PARITY BIT'
336 if self.options['parity'] == 'none':
337 self.state[rxtx] = 'GET STOP BITS'
339 def format_value(self, v):
340 # Format value 'v' according to configured options.
341 # Reflects the user selected kind of representation, as well as
342 # the number of data bits in the UART frames.
344 fmt, bits = self.options['format'], self.options['data_bits']
346 # Assume "is printable" for values from 32 to including 126,
347 # below 32 is "control" and thus not printable, above 127 is
348 # "not ASCII" in its strict sense, 127 (DEL) is not printable,
349 # fall back to hex representation for non-printables.
351 if v in range(32, 126 + 1):
353 hexfmt = "[{:02X}]" if bits <= 8 else "[{:03X}]"
354 return hexfmt.format(v)
356 # Mere number to text conversion without prefix and padding
357 # for the "decimal" output format.
359 return "{:d}".format(v)
361 # Padding with leading zeroes for hex/oct/bin formats, but
362 # without a prefix for density -- since the format is user
363 # specified, there is no ambiguity.
365 digits = (bits + 4 - 1) // 4
368 digits = (bits + 3 - 1) // 3
375 if fmtchar is not None:
376 fmt = "{{:0{:d}{:s}}}".format(digits, fmtchar)
381 def get_parity_bit(self, rxtx, signal):
382 self.paritybit[rxtx] = signal
384 if parity_ok(self.options['parity'], self.paritybit[rxtx],
385 self.datavalue[rxtx], self.options['data_bits']):
386 self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
387 self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
389 # TODO: Return expected/actual parity values.
390 self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
391 self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
392 self.frame_valid[rxtx] = False
394 self.state[rxtx] = 'GET STOP BITS'
396 # TODO: Currently only supports 1 stop bit.
397 def get_stop_bits(self, rxtx, signal):
398 self.stopbit1[rxtx] = signal
400 # Stop bits must be 1. If not, we report an error.
401 if self.stopbit1[rxtx] != 1:
402 self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
403 self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
404 self.frame_valid[rxtx] = False
406 self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
407 self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
409 # Pass the complete UART frame to upper layers.
410 es = self.samplenum + ceil(self.bit_width / 2.0)
411 self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
412 (self.datavalue[rxtx], self.frame_valid[rxtx])])
414 self.state[rxtx] = 'WAIT FOR START BIT'
415 self.idle_start[rxtx] = self.frame_start[rxtx] + self.frame_len_sample_count
417 def handle_break(self, rxtx):
418 self.putpse(self.frame_start[rxtx], self.samplenum,
420 self.putgse(self.frame_start[rxtx], self.samplenum,
421 [rxtx + 14, ['Break condition', 'Break', 'Brk', 'B']])
422 self.state[rxtx] = 'WAIT FOR START BIT'
424 def get_wait_cond(self, rxtx, inv):
425 # Return condititions that are suitable for Decoder.wait(). Those
426 # conditions either match the falling edge of the START bit, or
427 # the sample point of the next bit time.
428 state = self.state[rxtx]
429 if state == 'WAIT FOR START BIT':
430 return {rxtx: 'r' if inv else 'f'}
431 if state == 'GET START BIT':
433 elif state == 'GET DATA BITS':
434 bitnum = 1 + self.cur_data_bit[rxtx]
435 elif state == 'GET PARITY BIT':
436 bitnum = 1 + self.options['data_bits']
437 elif state == 'GET STOP BITS':
438 bitnum = 1 + self.options['data_bits']
439 bitnum += 0 if self.options['parity'] == 'none' else 1
440 want_num = ceil(self.get_sample_point(rxtx, bitnum))
441 return {'skip': want_num - self.samplenum}
443 def get_idle_cond(self, rxtx, inv):
444 # Return a condition that corresponds to the (expected) end of
445 # the next frame, assuming that it will be an "idle frame"
446 # (constant high input level for the frame's length).
447 if self.idle_start[rxtx] is None:
449 end_of_frame = self.idle_start[rxtx] + self.frame_len_sample_count
450 if end_of_frame < self.samplenum:
452 return {'skip': end_of_frame - self.samplenum}
454 def inspect_sample(self, rxtx, signal, inv):
455 # Inspect a sample returned by .wait() for the specified UART line.
459 state = self.state[rxtx]
460 if state == 'WAIT FOR START BIT':
461 self.wait_for_start_bit(rxtx, signal)
462 elif state == 'GET START BIT':
463 self.get_start_bit(rxtx, signal)
464 elif state == 'GET DATA BITS':
465 self.get_data_bits(rxtx, signal)
466 elif state == 'GET PARITY BIT':
467 self.get_parity_bit(rxtx, signal)
468 elif state == 'GET STOP BITS':
469 self.get_stop_bits(rxtx, signal)
471 def inspect_edge(self, rxtx, signal, inv):
472 # Inspect edges, independently from traffic, to detect break conditions.
476 # Signal went low. Start another interval.
477 self.break_start[rxtx] = self.samplenum
479 # Signal went high. Was there an extended period with low signal?
480 if self.break_start[rxtx] is None:
482 diff = self.samplenum - self.break_start[rxtx]
483 if diff >= self.break_min_sample_count:
484 self.handle_break(rxtx)
485 self.break_start[rxtx] = None
487 def inspect_idle(self, rxtx, signal, inv):
488 # Check each edge and each period of stable input (either level).
489 # Can derive the "idle frame period has passed" condition.
493 # Low input, cease inspection.
494 self.idle_start[rxtx] = None
496 # High input, either just reached, or still stable.
497 if self.idle_start[rxtx] is None:
498 self.idle_start[rxtx] = self.samplenum
499 diff = self.samplenum - self.idle_start[rxtx]
500 if diff < self.frame_len_sample_count:
502 ss, es = self.idle_start[rxtx], self.samplenum
503 self.putpse(ss, es, ['IDLE', rxtx, 0])
504 self.idle_start[rxtx] = self.samplenum
507 if not self.samplerate:
508 raise SamplerateError('Cannot decode without samplerate.')
510 has_pin = [self.has_channel(ch) for ch in (RX, TX)]
511 if not True in has_pin:
512 raise ChannelError('Need at least one of TX or RX pins.')
515 inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes']
516 cond_data_idx = [None] * len(has_pin)
518 # Determine the number of samples for a complete frame's time span.
519 # A period of low signal (at least) that long is a break condition.
520 frame_samples = 1 # START
521 frame_samples += self.options['data_bits']
522 frame_samples += 0 if self.options['parity'] == 'none' else 1
523 frame_samples += self.options['stop_bits']
524 frame_samples *= self.bit_width
525 self.frame_len_sample_count = ceil(frame_samples)
526 self.break_min_sample_count = self.frame_len_sample_count
527 cond_edge_idx = [None] * len(has_pin)
528 cond_idle_idx = [None] * len(has_pin)
533 cond_data_idx[RX] = len(conds)
534 conds.append(self.get_wait_cond(RX, inv[RX]))
535 cond_edge_idx[RX] = len(conds)
536 conds.append({RX: 'e'})
537 cond_idle_idx[RX] = None
538 idle_cond = self.get_idle_cond(RX, inv[RX])
540 cond_idle_idx[RX] = len(conds)
541 conds.append(idle_cond)
543 cond_data_idx[TX] = len(conds)
544 conds.append(self.get_wait_cond(TX, inv[TX]))
545 cond_edge_idx[TX] = len(conds)
546 conds.append({TX: 'e'})
547 cond_idle_idx[TX] = None
548 idle_cond = self.get_idle_cond(TX, inv[TX])
550 cond_idle_idx[TX] = len(conds)
551 conds.append(idle_cond)
552 (rx, tx) = self.wait(conds)
553 if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]:
554 self.inspect_sample(RX, rx, inv[RX])
555 if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]:
556 self.inspect_edge(RX, rx, inv[RX])
557 self.inspect_idle(RX, rx, inv[RX])
558 if cond_idle_idx[RX] is not None and self.matched[cond_idle_idx[RX]]:
559 self.inspect_idle(RX, rx, inv[RX])
560 if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]:
561 self.inspect_sample(TX, tx, inv[TX])
562 if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]:
563 self.inspect_edge(TX, tx, inv[TX])
564 self.inspect_idle(TX, tx, inv[TX])
565 if cond_idle_idx[TX] is not None and self.matched[cond_idle_idx[TX]]:
566 self.inspect_idle(TX, tx, inv[TX])