2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
27 [<ptype>, <rxtx>, <pdata>]
29 This is the list of <ptype>s and their respective <pdata> values:
30 - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
31 - 'DATA': The data is the (integer) value of the UART data. Valid values
32 range from 0 to 512 (as the data can be up to 9 bits in size).
33 - 'DATABITS': List of data bits and their ss/es numbers.
34 - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
35 - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
36 - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
37 - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
38 - 'PARITY ERROR': The data is a tuple with two entries. The first one is
39 the expected parity value, the second is the actual parity value.
42 The <rxtx> field is 0 for RX packets, 1 for TX packets.
45 # Used for differentiating between the two data directions.
49 # Given a parity type to check (odd, even, zero, one), the value of the
50 # parity bit, the value of the data, and the length of the data (5-9 bits,
51 # usually 8 bits) return True if the parity is correct, False otherwise.
52 # 'none' is _not_ allowed as value for 'parity_type'.
53 def parity_ok(parity_type, parity_bit, data, num_data_bits):
55 # Handle easy cases first (parity bit is always 1 or 0).
56 if parity_type == 'zero':
57 return parity_bit == 0
58 elif parity_type == 'one':
59 return parity_bit == 1
61 # Count number of 1 (high) bits in the data (and the parity bit itself!).
62 ones = bin(data).count('1') + parity_bit
64 # Check for odd/even parity.
65 if parity_type == 'odd':
66 return (ones % 2) == 1
67 elif parity_type == 'even':
68 return (ones % 2) == 0
70 raise Exception('Invalid parity type: %d' % parity_type)
72 class SamplerateError(Exception):
75 class Decoder(srd.Decoder):
79 longname = 'Universal Asynchronous Receiver/Transmitter'
80 desc = 'Asynchronous, serial bus.'
85 # Allow specifying only one of the signals, e.g. if only one data
86 # direction exists (or is relevant).
87 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
88 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
91 {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
92 {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8,
93 'values': (5, 6, 7, 8, 9)},
94 {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none',
95 'values': ('none', 'odd', 'even', 'zero', 'one')},
96 {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes',
97 'values': ('yes', 'no')},
98 {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0,
99 'values': (0.0, 0.5, 1.0, 1.5)},
100 {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
101 'values': ('lsb-first', 'msb-first')},
102 {'id': 'format', 'desc': 'Data format', 'default': 'ascii',
103 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
104 # TODO: Options to invert the signal(s).
107 ('rx-data', 'RX data'),
108 ('tx-data', 'TX data'),
109 ('rx-start', 'RX start bits'),
110 ('tx-start', 'TX start bits'),
111 ('rx-parity-ok', 'RX parity OK bits'),
112 ('tx-parity-ok', 'TX parity OK bits'),
113 ('rx-parity-err', 'RX parity error bits'),
114 ('tx-parity-err', 'TX parity error bits'),
115 ('rx-stop', 'RX stop bits'),
116 ('tx-stop', 'TX stop bits'),
117 ('rx-warnings', 'RX warnings'),
118 ('tx-warnings', 'TX warnings'),
119 ('rx-data-bits', 'RX data bits'),
120 ('tx-data-bits', 'TX data bits'),
123 ('rx-data', 'RX', (0, 2, 4, 6, 8)),
124 ('rx-data-bits', 'RX bits', (12,)),
125 ('rx-warnings', 'RX warnings', (10,)),
126 ('tx-data', 'TX', (1, 3, 5, 7, 9)),
127 ('tx-data-bits', 'TX bits', (13,)),
128 ('tx-warnings', 'TX warnings', (11,)),
133 ('rxtx', 'RX/TX dump'),
136 def putx(self, rxtx, data):
137 s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
138 self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data)
140 def putpx(self, rxtx, data):
141 s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
142 self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data)
144 def putg(self, data):
145 s, halfbit = self.samplenum, int(self.bit_width / 2)
146 self.put(s - halfbit, s + halfbit, self.out_ann, data)
148 def putp(self, data):
149 s, halfbit = self.samplenum, int(self.bit_width / 2)
150 self.put(s - halfbit, s + halfbit, self.out_python, data)
152 def putbin(self, rxtx, data):
153 s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
154 self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data)
156 def __init__(self, **kwargs):
157 self.samplerate = None
159 self.frame_start = [-1, -1]
160 self.startbit = [-1, -1]
161 self.cur_data_bit = [0, 0]
162 self.databyte = [0, 0]
163 self.paritybit = [-1, -1]
164 self.stopbit1 = [-1, -1]
165 self.startsample = [-1, -1]
166 self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
168 self.oldpins = [1, 1]
169 self.databits = [[], []]
172 self.out_python = self.register(srd.OUTPUT_PYTHON)
173 self.out_bin = self.register(srd.OUTPUT_BINARY)
174 self.out_ann = self.register(srd.OUTPUT_ANN)
176 def metadata(self, key, value):
177 if key == srd.SRD_CONF_SAMPLERATE:
178 self.samplerate = value;
179 # The width of one UART bit in number of samples.
180 self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
182 # Return true if we reached the middle of the desired bit, false otherwise.
183 def reached_bit(self, rxtx, bitnum):
184 # bitpos is the samplenumber which is in the middle of the
185 # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
186 # (if used) or the first stop bit, and so on).
187 bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0)
188 bitpos += bitnum * self.bit_width
189 if self.samplenum >= bitpos:
193 def reached_bit_last(self, rxtx, bitnum):
194 bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width)
195 if self.samplenum >= bitpos:
199 def wait_for_start_bit(self, rxtx, old_signal, signal):
200 # The start bit is always 0 (low). As the idle UART (and the stop bit)
201 # level is 1 (high), the beginning of a start bit is a falling edge.
202 if not (old_signal == 1 and signal == 0):
205 # Save the sample number where the start bit begins.
206 self.frame_start[rxtx] = self.samplenum
208 self.state[rxtx] = 'GET START BIT'
210 def get_start_bit(self, rxtx, signal):
211 # Skip samples until we're in the middle of the start bit.
212 if not self.reached_bit(rxtx, 0):
215 self.startbit[rxtx] = signal
217 # The startbit must be 0. If not, we report an error.
218 if self.startbit[rxtx] != 0:
219 self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
220 # TODO: Abort? Ignore rest of the frame?
222 self.cur_data_bit[rxtx] = 0
223 self.databyte[rxtx] = 0
224 self.startsample[rxtx] = -1
226 self.state[rxtx] = 'GET DATA BITS'
228 self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
229 self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
231 def get_data_bits(self, rxtx, signal):
232 # Skip samples until we're in the middle of the desired data bit.
233 if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1):
236 # Save the sample number of the middle of the first data bit.
237 if self.startsample[rxtx] == -1:
238 self.startsample[rxtx] = self.samplenum
240 # Get the next data bit in LSB-first or MSB-first fashion.
241 if self.options['bit_order'] == 'lsb-first':
242 self.databyte[rxtx] >>= 1
243 self.databyte[rxtx] |= \
244 (signal << (self.options['num_data_bits'] - 1))
245 elif self.options['bit_order'] == 'msb-first':
246 self.databyte[rxtx] <<= 1
247 self.databyte[rxtx] |= (signal << 0)
249 raise Exception('Invalid bit order value: %s',
250 self.options['bit_order'])
252 self.putg([rxtx + 12, ['%d' % signal]])
254 # Store individual data bits and their start/end samplenumbers.
255 s, halfbit = self.samplenum, int(self.bit_width / 2)
256 self.databits[rxtx].append([signal, s - halfbit, s + halfbit])
258 # Return here, unless we already received all data bits.
259 if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
260 self.cur_data_bit[rxtx] += 1
263 self.state[rxtx] = 'GET PARITY BIT'
265 self.putpx(rxtx, ['DATABITS', rxtx, self.databits[rxtx]])
266 self.putpx(rxtx, ['DATA', rxtx, self.databyte[rxtx]])
268 b, f = self.databyte[rxtx], self.options['format']
270 c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b
271 self.putx(rxtx, [rxtx, [c]])
273 self.putx(rxtx, [rxtx, [str(b)]])
275 self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]])
277 self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
279 self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
281 raise Exception('Invalid data format option: %s' % f)
283 self.putbin(rxtx, (rxtx, bytes([b])))
284 self.putbin(rxtx, (2, bytes([b])))
286 self.databits = [[], []]
288 def get_parity_bit(self, rxtx, signal):
289 # If no parity is used/configured, skip to the next state immediately.
290 if self.options['parity_type'] == 'none':
291 self.state[rxtx] = 'GET STOP BITS'
294 # Skip samples until we're in the middle of the parity bit.
295 if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1):
298 self.paritybit[rxtx] = signal
300 self.state[rxtx] = 'GET STOP BITS'
302 if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
303 self.databyte[rxtx], self.options['num_data_bits']):
304 self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
305 self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
307 # TODO: Return expected/actual parity values.
308 self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
309 self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
311 # TODO: Currently only supports 1 stop bit.
312 def get_stop_bits(self, rxtx, signal):
313 # Skip samples until we're in the middle of the stop bit(s).
314 skip_parity = 0 if self.options['parity_type'] == 'none' else 1
315 b = self.options['num_data_bits'] + 1 + skip_parity
316 if not self.reached_bit(rxtx, b):
319 self.stopbit1[rxtx] = signal
321 # Stop bits must be 1. If not, we report an error.
322 if self.stopbit1[rxtx] != 1:
323 self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
324 self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']])
325 # TODO: Abort? Ignore the frame? Other?
327 self.state[rxtx] = 'WAIT FOR START BIT'
329 self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
330 self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
332 def decode(self, ss, es, data):
333 if not self.samplerate:
334 raise SamplerateError('Cannot decode without samplerate.')
335 for (self.samplenum, pins) in data:
337 # Note: Ignoring identical samples here for performance reasons
338 # is not possible for this PD, at least not in the current state.
339 # if self.oldpins == pins:
341 self.oldpins, (rx, tx) = pins, pins
343 # Either RX or TX (but not both) can be omitted.
344 has_pin = [rx in (0, 1), tx in (0, 1)]
345 if has_pin == [False, False]:
346 raise Exception('Either TX or RX (or both) pins required.')
349 for rxtx in (RX, TX):
350 # Don't try to handle RX (or TX) if not supplied.
351 if not has_pin[rxtx]:
354 signal = rx if (rxtx == RX) else tx
356 if self.state[rxtx] == 'WAIT FOR START BIT':
357 self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
358 elif self.state[rxtx] == 'GET START BIT':
359 self.get_start_bit(rxtx, signal)
360 elif self.state[rxtx] == 'GET DATA BITS':
361 self.get_data_bits(rxtx, signal)
362 elif self.state[rxtx] == 'GET PARITY BIT':
363 self.get_parity_bit(rxtx, signal)
364 elif self.state[rxtx] == 'GET STOP BITS':
365 self.get_stop_bits(rxtx, signal)
367 # Save current RX/TX values for the next round.
368 self.oldbit[rxtx] = signal