2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
27 [<packet-type>, <rxtx>, <packet-data>]
29 This is the list of <packet-type>s and their respective <packet-data>:
30 - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
31 - 'DATA': The data is the (integer) value of the UART data. Valid values
32 range from 0 to 512 (as the data can be up to 9 bits in size).
33 - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
34 - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
35 - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
36 - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
37 - 'PARITY ERROR': The data is a tuple with two entries. The first one is
38 the expected parity value, the second is the actual parity value.
41 The <rxtx> field is 0 for RX packets, 1 for TX packets.
44 # Used for differentiating between the two data directions.
48 # Given a parity type to check (odd, even, zero, one), the value of the
49 # parity bit, the value of the data, and the length of the data (5-9 bits,
50 # usually 8 bits) return True if the parity is correct, False otherwise.
51 # 'none' is _not_ allowed as value for 'parity_type'.
52 def parity_ok(parity_type, parity_bit, data, num_data_bits):
54 # Handle easy cases first (parity bit is always 1 or 0).
55 if parity_type == 'zero':
56 return parity_bit == 0
57 elif parity_type == 'one':
58 return parity_bit == 1
60 # Count number of 1 (high) bits in the data (and the parity bit itself!).
61 ones = bin(data).count('1') + parity_bit
63 # Check for odd/even parity.
64 if parity_type == 'odd':
65 return (ones % 2) == 1
66 elif parity_type == 'even':
67 return (ones % 2) == 0
69 raise Exception('Invalid parity type: %d' % parity_type)
71 class Decoder(srd.Decoder):
75 longname = 'Universal Asynchronous Receiver/Transmitter'
76 desc = 'Asynchronous, serial bus.'
82 # Allow specifying only one of the signals, e.g. if only one data
83 # direction exists (or is relevant).
84 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
85 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
88 'baudrate': ['Baud rate', 115200],
89 'num_data_bits': ['Data bits', 8], # Valid: 5-9.
90 'parity_type': ['Parity type', 'none'],
91 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
92 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
93 'bit_order': ['Bit order', 'lsb-first'],
94 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin
95 # TODO: Options to invert the signal(s).
98 ['rx-data', 'RX data'],
99 ['tx-data', 'TX data'],
100 ['rx-start-bits', 'RX start bits'],
101 ['tx-start-bits', 'TX start bits'],
102 ['rx-parity-bits', 'RX parity bits'],
103 ['tx-parity-bits', 'TX parity bits'],
104 ['rx-stop-bits', 'RX stop bits'],
105 ['tx-stop-bits', 'TX stop bits'],
106 ['rx-warnings', 'RX warnings'],
107 ['tx-warnings', 'TX warnings'],
110 ('rx-data', 'RX', (0, 2, 4, 6)),
111 ('tx-data', 'TX', (1, 3, 5, 7)),
112 ('rx-warnings', 'RX warnings', (8,)),
113 ('tx-warnings', 'TX warnings', (9,)),
118 ('rxtx', 'RX/TX dump'),
121 def putx(self, rxtx, data):
122 s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
123 self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data)
125 def putg(self, data):
126 s, halfbit = self.samplenum, int(self.bit_width / 2)
127 self.put(s - halfbit, s + halfbit, self.out_ann, data)
129 def putp(self, data):
130 s, halfbit = self.samplenum, int(self.bit_width / 2)
131 self.put(s - halfbit, s + halfbit, self.out_python, data)
133 def putbin(self, rxtx, data):
134 s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
135 self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data)
137 def __init__(self, **kwargs):
138 self.samplerate = None
140 self.frame_start = [-1, -1]
141 self.startbit = [-1, -1]
142 self.cur_data_bit = [0, 0]
143 self.databyte = [0, 0]
144 self.paritybit = [-1, -1]
145 self.stopbit1 = [-1, -1]
146 self.startsample = [-1, -1]
147 self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
149 self.oldpins = [1, 1]
152 self.out_python = self.register(srd.OUTPUT_PYTHON)
153 self.out_bin = self.register(srd.OUTPUT_BINARY)
154 self.out_ann = self.register(srd.OUTPUT_ANN)
156 def metadata(self, key, value):
157 if key == srd.SRD_CONF_SAMPLERATE:
158 self.samplerate = value;
159 # The width of one UART bit in number of samples.
160 self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
162 # Return true if we reached the middle of the desired bit, false otherwise.
163 def reached_bit(self, rxtx, bitnum):
164 # bitpos is the samplenumber which is in the middle of the
165 # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
166 # (if used) or the first stop bit, and so on).
167 bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0)
168 bitpos += bitnum * self.bit_width
169 if self.samplenum >= bitpos:
173 def reached_bit_last(self, rxtx, bitnum):
174 bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width)
175 if self.samplenum >= bitpos:
179 def wait_for_start_bit(self, rxtx, old_signal, signal):
180 # The start bit is always 0 (low). As the idle UART (and the stop bit)
181 # level is 1 (high), the beginning of a start bit is a falling edge.
182 if not (old_signal == 1 and signal == 0):
185 # Save the sample number where the start bit begins.
186 self.frame_start[rxtx] = self.samplenum
188 self.state[rxtx] = 'GET START BIT'
190 def get_start_bit(self, rxtx, signal):
191 # Skip samples until we're in the middle of the start bit.
192 if not self.reached_bit(rxtx, 0):
195 self.startbit[rxtx] = signal
197 # The startbit must be 0. If not, we report an error.
198 if self.startbit[rxtx] != 0:
199 self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
200 # TODO: Abort? Ignore rest of the frame?
202 self.cur_data_bit[rxtx] = 0
203 self.databyte[rxtx] = 0
204 self.startsample[rxtx] = -1
206 self.state[rxtx] = 'GET DATA BITS'
208 self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
209 self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
211 def get_data_bits(self, rxtx, signal):
212 # Skip samples until we're in the middle of the desired data bit.
213 if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1):
216 # Save the sample number of the middle of the first data bit.
217 if self.startsample[rxtx] == -1:
218 self.startsample[rxtx] = self.samplenum
220 # Get the next data bit in LSB-first or MSB-first fashion.
221 if self.options['bit_order'] == 'lsb-first':
222 self.databyte[rxtx] >>= 1
223 self.databyte[rxtx] |= \
224 (signal << (self.options['num_data_bits'] - 1))
225 elif self.options['bit_order'] == 'msb-first':
226 self.databyte[rxtx] <<= 1
227 self.databyte[rxtx] |= (signal << 0)
229 raise Exception('Invalid bit order value: %s',
230 self.options['bit_order'])
232 # Return here, unless we already received all data bits.
233 if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
234 self.cur_data_bit[rxtx] += 1
237 self.state[rxtx] = 'GET PARITY BIT'
239 self.putp(['DATA', rxtx, self.databyte[rxtx]])
241 b, f = self.databyte[rxtx], self.options['format']
243 c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b
244 self.putx(rxtx, [rxtx, [c]])
246 self.putx(rxtx, [rxtx, [str(b)]])
248 self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]])
250 self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
252 self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
254 raise Exception('Invalid data format option: %s' % f)
256 self.putbin(rxtx, (rxtx, bytes([b])))
257 self.putbin(rxtx, (2, bytes([b])))
259 def get_parity_bit(self, rxtx, signal):
260 # If no parity is used/configured, skip to the next state immediately.
261 if self.options['parity_type'] == 'none':
262 self.state[rxtx] = 'GET STOP BITS'
265 # Skip samples until we're in the middle of the parity bit.
266 if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1):
269 self.paritybit[rxtx] = signal
271 self.state[rxtx] = 'GET STOP BITS'
273 if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
274 self.databyte[rxtx], self.options['num_data_bits']):
275 self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
276 self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
278 # TODO: Return expected/actual parity values.
279 self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
280 self.putg([rxtx + 8, ['Parity error', 'Parity err', 'PE']])
282 # TODO: Currently only supports 1 stop bit.
283 def get_stop_bits(self, rxtx, signal):
284 # Skip samples until we're in the middle of the stop bit(s).
285 skip_parity = 0 if self.options['parity_type'] == 'none' else 1
286 b = self.options['num_data_bits'] + 1 + skip_parity
287 if not self.reached_bit(rxtx, b):
290 self.stopbit1[rxtx] = signal
292 # Stop bits must be 1. If not, we report an error.
293 if self.stopbit1[rxtx] != 1:
294 self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
295 self.putg([rxtx + 6, ['Frame error', 'Frame err', 'FE']])
296 # TODO: Abort? Ignore the frame? Other?
298 self.state[rxtx] = 'WAIT FOR START BIT'
300 self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
301 self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
303 def decode(self, ss, es, data):
304 if self.samplerate is None:
305 raise Exception("Cannot decode without samplerate.")
306 for (self.samplenum, pins) in data:
308 # Note: Ignoring identical samples here for performance reasons
309 # is not possible for this PD, at least not in the current state.
310 # if self.oldpins == pins:
312 self.oldpins, (rx, tx) = pins, pins
314 # Either RX or TX (but not both) can be omitted.
315 has_pin = [rx in (0, 1), tx in (0, 1)]
316 if has_pin == [False, False]:
317 raise Exception('Either TX or RX (or both) pins required.')
320 for rxtx in (RX, TX):
321 # Don't try to handle RX (or TX) if not supplied.
322 if not has_pin[rxtx]:
325 signal = rx if (rxtx == RX) else tx
327 if self.state[rxtx] == 'WAIT FOR START BIT':
328 self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
329 elif self.state[rxtx] == 'GET START BIT':
330 self.get_start_bit(rxtx, signal)
331 elif self.state[rxtx] == 'GET DATA BITS':
332 self.get_data_bits(rxtx, signal)
333 elif self.state[rxtx] == 'GET PARITY BIT':
334 self.get_parity_bit(rxtx, signal)
335 elif self.state[rxtx] == 'GET STOP BITS':
336 self.get_stop_bits(rxtx, signal)
338 raise Exception('Invalid state: %s' % self.state[rxtx])
340 # Save current RX/TX values for the next round.
341 self.oldbit[rxtx] = signal