2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # UART protocol decoder
26 # Universal Asynchronous Receiver Transmitter (UART) is a simple serial
27 # communication protocol which allows two devices to talk to each other.
29 # It uses just two data signals and a ground (GND) signal:
30 # - RX/RXD: Receive signal
31 # - TX/TXD: Transmit signal
33 # The protocol is asynchronous, i.e., there is no dedicated clock signal.
34 # Rather, both devices have to agree on a baudrate (number of bits to be
35 # transmitted per second) beforehand. Baudrates can be arbitrary in theory,
36 # but usually the choice is limited by the hardware UARTs that are used.
37 # Common values are 9600 or 115200.
39 # The protocol allows full-duplex transmission, i.e. both devices can send
40 # data at the same time. However, unlike SPI (which is always full-duplex,
41 # i.e., each send operation is automatically also a receive operation), UART
42 # allows one-way communication, too. In such a case only one signal (and GND)
45 # The data is sent over the TX line in so-called 'frames', which consist of:
46 # - Exactly one start bit (always 0/low).
47 # - Between 5 and 9 data bits.
48 # - An (optional) parity bit.
49 # - One or more stop bit(s).
51 # The idle state of the RX/TX line is 1/high. As the start bit is 0/low, the
52 # receiver can continually monitor its RX line for a falling edge, in order
53 # to detect the start bit.
55 # Once detected, it can (due to the agreed-upon baudrate and thus the known
56 # width/duration of one UART bit) sample the state of the RX line "in the
57 # middle" of each (start/data/parity/stop) bit it wants to analyze.
59 # It is configurable whether there is a parity bit in a frame, and if yes,
60 # which type of parity is used:
61 # - None: No parity bit is included.
62 # - Odd: The number of 1 bits in the data (and parity bit itself) is odd.
63 # - Even: The number of 1 bits in the data (and parity bit itself) is even.
64 # - Mark/one: The parity bit is always 1/high (also called 'mark state').
65 # - Space/zero: The parity bit is always 0/low (also called 'space state').
67 # It is also configurable how many stop bits are to be used:
68 # - 1 stop bit (most common case)
70 # - 1.5 stop bits (i.e., one stop bit, but 1.5 times the UART bit width)
71 # - 0.5 stop bits (i.e., one stop bit, but 0.5 times the UART bit width)
73 # The bit order of the 5-9 data bits is LSB-first.
75 # Possible special cases:
76 # - One or both data lines could be inverted, which also means that the idle
77 # state of the signal line(s) is low instead of high.
78 # - Only the data bits on one or both data lines (and the parity bit) could
79 # be inverted (but the start/stop bits remain non-inverted).
80 # - The bit order could be MSB-first instead of LSB-first.
81 # - The baudrate could change in the middle of the communication. This only
82 # happens in very special cases, and can only work if both devices know
83 # to which baudrate they are to switch, and when.
84 # - Theoretically, the baudrate on RX and the one on TX could also be
85 # different, but that's a very obscure case and probably doesn't happen
86 # very often in practice.
89 # - If there is a parity bit, but it doesn't match the expected parity,
90 # this is called a 'parity error'.
91 # - If there are no stop bit(s), that's called a 'frame error'.
98 # Protocol output format:
99 # put(<startsample>, <endsample>, self.out_proto, <packet>)
101 # The <packet> is a list with two entries:
102 # [<packet-type>, <packet-data>]
104 # Valid packet-type values: T_START, T_DATA, T_PARITY, T_STOP, T_INVALID_START,
105 # T_INVALID_STOP, T_PARITY_ERROR
107 # The packet-data field has the following format and meaning:
108 # - T_START: The data is the (integer) value of the start bit (0 or 1).
109 # - T_DATA: The data is the (integer) value of the UART data. Valid values
110 # range from 0 to 512 (as the data can be up to 9 bits in size).
111 # - T_PARITY: The data is the (integer) value of the parity bit (0 or 1).
112 # - T_STOP: The data is the (integer) value of the stop bit (0 or 1).
113 # - T_INVALID_START: The data is the (integer) value of the start bit (0 or 1).
114 # - T_INVALID_STOP: The data is the (integer) value of the stop bit (0 or 1).
115 # - T_PARITY_ERROR: The data is a tuple with two entries. The first one is
116 # the expected parity value, the second is the actual parity value.
123 # [T_INVALID_START, 1]
124 # [T_INVALID_STOP, 0]
125 # [T_PARITY_ERROR, (0, 1)]
128 import sigrokdecode as srd
131 WAIT_FOR_START_BIT = 0
154 # Annotation feed formats
161 # Protocol output packet types
170 # Given a parity type to check (odd, even, zero, one), the value of the
171 # parity bit, the value of the data, and the length of the data (5-9 bits,
172 # usually 8 bits) return True if the parity is correct, False otherwise.
173 # PARITY_NONE is _not_ allowed as value for 'parity_type'.
174 def parity_ok(parity_type, parity_bit, data, num_data_bits):
176 # Handle easy cases first (parity bit is always 1 or 0).
177 if parity_type == PARITY_ZERO:
178 return parity_bit == 0
179 elif parity_type == PARITY_ONE:
180 return parity_bit == 1
182 # Count number of 1 (high) bits in the data (and the parity bit itself!).
183 parity = bin(data).count('1') + parity_bit
185 # Check for odd/even parity.
186 if parity_type == PARITY_ODD:
187 return (parity % 2) == 1
188 elif parity_type == PARITY_EVEN:
189 return (parity % 2) == 0
191 raise Exception('Invalid parity type: %d' % parity_type)
193 class Decoder(srd.Decoder):
196 longname = 'Universal Asynchronous Receiver/Transmitter (UART)'
197 desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
199 author = 'Uwe Hermann'
200 email = 'uwe@hermann-uwe.de'
205 # Allow specifying only one of the signals, e.g. if only one data
206 # direction exists (or is relevant).
207 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
208 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
211 'baudrate': ['UART baud rate', 115200],
212 'num_data_bits': ['Data bits', 8], # Valid: 5-9.
213 'parity': ['Parity', PARITY_NONE],
214 'parity_check': ['Check parity', True],
215 'num_stop_bits': ['Stop bit(s)', STOP_BITS_1],
216 'bit_order': ['Bit order', LSB_FIRST],
217 # TODO: Options to invert the signal(s).
222 ["ASCII", "TODO: description"],
224 ["Decimal", "TODO: description"],
226 ["Hex", "TODO: description"],
228 ["Octal", "TODO: description"],
230 ["Bits", "TODO: description"],
233 def __init__(self, **kwargs):
234 # Set defaults, can be overridden in 'start'.
235 self.baudrate = 115200
236 self.num_data_bits = 8
237 self.parity = PARITY_NONE
238 self.check_parity = True
239 self.num_stop_bits = 1
240 self.bit_order = LSB_FIRST
243 self.frame_start = -1
245 self.cur_data_bit = 0
248 self.startsample = -1
251 self.staterx = WAIT_FOR_START_BIT
256 def start(self, metadata):
257 self.samplerate = metadata['samplerate']
258 self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
259 self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
262 ### self.baudrate = metadata['baudrate']
263 ### self.num_data_bits = metadata['num_data_bits']
264 ### self.parity = metadata['parity']
265 ### self.parity_check = metadata['parity_check']
266 ### self.num_stop_bits = metadata['num_stop_bits']
267 ### self.bit_order = metadata['bit_order']
269 # The width of one UART bit in number of samples.
270 self.bit_width = float(self.samplerate) / float(self.baudrate)
275 # Return true if we reached the middle of the desired bit, false otherwise.
276 def reached_bit(self, bitnum):
277 # bitpos is the samplenumber which is in the middle of the
278 # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
279 # (if used) or the first stop bit, and so on).
280 bitpos = self.frame_start + (self.bit_width / 2.0)
281 bitpos += bitnum * self.bit_width
282 if self.samplenum >= bitpos:
286 def reached_bit_last(self, bitnum):
287 bitpos = self.frame_start + ((bitnum + 1) * self.bit_width)
288 if self.samplenum >= bitpos:
292 def wait_for_start_bit(self, old_signal, signal):
293 # The start bit is always 0 (low). As the idle UART (and the stop bit)
294 # level is 1 (high), the beginning of a start bit is a falling edge.
295 if not (old_signal == 1 and signal == 0):
298 # Save the sample number where the start bit begins.
299 self.frame_start = self.samplenum
301 self.staterx = GET_START_BIT
303 def get_start_bit(self, signal):
304 # Skip samples until we're in the middle of the start bit.
305 if not self.reached_bit(0):
308 self.startbit = signal
310 # The startbit must be 0. If not, we report an error.
311 if self.startbit != 0:
312 self.put(self.frame_start, self.samplenum, self.out_proto,
313 [T_INVALID_START, self.startbit])
314 # TODO: Abort? Ignore rest of the frame?
316 self.cur_data_bit = 0
318 self.startsample = -1
320 self.staterx = GET_DATA_BITS
322 self.put(self.frame_start, self.samplenum, self.out_proto,
323 [T_START, self.startbit])
324 self.put(self.frame_start, self.samplenum, self.out_ann,
325 [ANN_ASCII, ['Start bit', 'Start', 'S']])
327 def get_data_bits(self, signal):
328 # Skip samples until we're in the middle of the desired data bit.
329 if not self.reached_bit(self.cur_data_bit + 1):
332 # Save the sample number where the data byte starts.
333 if self.startsample == -1:
334 self.startsample = self.samplenum
336 # Get the next data bit in LSB-first or MSB-first fashion.
337 if self.bit_order == LSB_FIRST:
339 self.databyte |= (signal << (self.num_data_bits - 1))
340 elif self.bit_order == MSB_FIRST:
342 self.databyte |= (signal << 0)
344 raise Exception('Invalid bit order value: %d', self.bit_order)
346 # Return here, unless we already received all data bits.
347 if self.cur_data_bit < self.num_data_bits - 1: # TODO? Off-by-one?
348 self.cur_data_bit += 1
351 self.staterx = GET_PARITY_BIT
353 self.put(self.startsample, self.samplenum - 1, self.out_proto,
354 [T_DATA, self.databyte])
356 self.put(self.startsample, self.samplenum - 1, self.out_ann,
357 [ANN_ASCII, [chr(self.databyte)]])
358 self.put(self.startsample, self.samplenum - 1, self.out_ann,
359 [ANN_DEC, [str(self.databyte)]])
360 self.put(self.startsample, self.samplenum - 1, self.out_ann,
361 [ANN_HEX, [hex(self.databyte), hex(self.databyte)[2:]]])
362 self.put(self.startsample, self.samplenum - 1, self.out_ann,
363 [ANN_OCT, [oct(self.databyte), oct(self.databyte)[2:]]])
364 self.put(self.startsample, self.samplenum - 1, self.out_ann,
365 [ANN_BITS, [bin(self.databyte), bin(self.databyte)[2:]]])
367 def get_parity_bit(self, signal):
368 # If no parity is used/configured, skip to the next state immediately.
369 if self.parity == PARITY_NONE:
370 self.staterx = GET_STOP_BITS
373 # Skip samples until we're in the middle of the parity bit.
374 if not self.reached_bit(self.num_data_bits + 1):
377 self.paritybit = signal
379 self.staterx = GET_STOP_BITS
381 if parity_ok(self.parity, self.paritybit, self.databyte,
384 self.put(self.samplenum, self.samplenum, self.out_proto,
385 [T_PARITY_BIT, self.paritybit])
386 self.put(self.samplenum, self.samplenum, self.out_ann,
387 [ANN_ASCII, ['Parity bit', 'Parity', 'P']])
390 # TODO: Return expected/actual parity values.
391 self.put(self.samplenum, self.samplenum, self.out_proto,
392 [T_PARITY_ERROR, (0, 1)]) # FIXME: Dummy tuple...
393 self.put(self.samplenum, self.samplenum, self.out_ann,
394 [ANN_ASCII, ['Parity error', 'Parity err', 'PE']])
396 # TODO: Currently only supports 1 stop bit.
397 def get_stop_bits(self, signal):
398 # Skip samples until we're in the middle of the stop bit(s).
399 skip_parity = 0 if self.parity == PARITY_NONE else 1
400 if not self.reached_bit(self.num_data_bits + 1 + skip_parity):
403 self.stopbit1 = signal
405 # Stop bits must be 1. If not, we report an error.
406 if self.stopbit1 != 1:
407 self.put(self.frame_start, self.samplenum, self.out_proto,
408 [T_INVALID_STOP, self.stopbit1])
409 # TODO: Abort? Ignore the frame? Other?
411 self.staterx = WAIT_FOR_START_BIT
414 self.put(self.samplenum, self.samplenum, self.out_proto,
415 [T_STOP, self.stopbit1])
416 self.put(self.samplenum, self.samplenum, self.out_ann,
417 [ANN_ASCII, ['Stop bit', 'Stop', 'P']])
419 def decode(self, timeoffset, duration, data): # TODO
420 # for (samplenum, (rx, tx)) in data:
421 for (samplenum, (rx,)) in data:
423 # TODO: Start counting at 0 or 1? Increase before or after?
426 # First sample: Save RX/TX value.
427 if self.oldrx == None:
428 # Get RX/TX bit values (0/1 for low/high) of the first sample.
434 if self.staterx == WAIT_FOR_START_BIT:
435 self.wait_for_start_bit(self.oldrx, rx)
436 elif self.staterx == GET_START_BIT:
437 self.get_start_bit(rx)
438 elif self.staterx == GET_DATA_BITS:
439 self.get_data_bits(rx)
440 elif self.staterx == GET_PARITY_BIT:
441 self.get_parity_bit(rx)
442 elif self.staterx == GET_STOP_BITS:
443 self.get_stop_bits(rx)
445 raise Exception('Invalid state: %s' % self.staterx)
447 # Save current RX/TX values for the next round.
452 # self.put(0, 0, self.out_proto, proto)
454 # self.put(0, 0, self.out_ann, ann)