2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2016 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
26 # Don't forget to keep this in sync with 'cmds' is lists.py.
28 WRSR, PP, READ, WRDI, RDSR, WREN, FAST_READ, SE, RDSCUR, WRSCUR, \
29 RDSR2, CE, ESRY, DSRY, REMS, RDID, RDP_RES, CP, ENSO, DP, READ2X, \
30 EXSO, CE2, BE, REMS2, \
31 BIT, FIELD, WARN = range(L + 3)
33 def cmd_annotation_classes():
34 return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()])
36 def decode_dual_bytes(sio0, sio1):
37 # Given a byte in SIO0 (MOSI) of even bits and a byte in
38 # SIO1 (MISO) of odd bits, return a tuple of two bytes.
39 def combine_byte(even, odd):
43 result |= 1 << (bit*2)
45 result |= 1 << ((bit*2) + 1)
47 return (combine_byte(sio0 >> 4, sio1 >> 4), combine_byte(sio0, sio1))
49 def decode_status_reg(data):
50 # TODO: Additional per-bit(s) self.put() calls with correct start/end.
52 # Bits[0:0]: WIP (write in progress)
53 s = 'W' if (data & (1 << 0)) else 'No w'
54 ret = '%srite operation in progress.\n' % s
56 # Bits[1:1]: WEL (write enable latch)
57 s = '' if (data & (1 << 1)) else 'not '
58 ret += 'Internal write enable latch is %sset.\n' % s
60 # Bits[5:2]: Block protect bits
61 # TODO: More detailed decoding (chip-dependent).
62 ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)
64 # Bits[6:6]: Continuously program mode (CP mode)
65 s = '' if (data & (1 << 6)) else 'not '
66 ret += 'Device is %sin continuously program mode (CP mode).\n' % s
68 # Bits[7:7]: SRWD (status register write disable)
69 s = 'not ' if (data & (1 << 7)) else ''
70 ret += 'Status register writes are %sallowed.\n' % s
74 class Decoder(srd.Decoder):
78 longname = 'SPI flash chips'
79 desc = 'xx25 series SPI (NOR) flash chip protocol.'
82 outputs = ['spiflash']
83 annotations = cmd_annotation_classes() + (
86 ('warning', 'Warning'),
89 ('bits', 'Bits', (L + 0,)),
90 ('fields', 'Fields', (L + 1,)),
91 ('commands', 'Commands', tuple(range(len(cmds)))),
92 ('warnings', 'Warnings', (L + 2,)),
95 {'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0],
96 'values': tuple(chips.keys())},
97 {'id': 'format', 'desc': 'Data format', 'default': 'hex',
98 'values': ('hex', 'ascii')},
103 self.on_end_transaction = None
104 self.end_current_transaction()
106 # Build dict mapping command keys to handler functions. Each
107 # command in 'cmds' (defined in lists.py) has a matching
108 # handler self.handle_<shortname>.
109 def get_handler(cmd):
110 s = 'handle_%s' % cmds[cmd][0].lower().replace('/', '_')
111 return getattr(self, s)
112 self.cmd_handlers = dict((cmd, get_handler(cmd)) for cmd in cmds.keys())
114 def end_current_transaction(self):
115 if self.on_end_transaction is not None: # Callback for CS# transition.
116 self.on_end_transaction()
117 self.on_end_transaction = None
124 self.out_ann = self.register(srd.OUTPUT_ANN)
125 self.chip = chips[self.options['chip']]
126 self.vendor = self.options['chip'].split('_')[0]
128 def putx(self, data):
129 # Simplification, most annotations span exactly one SPI byte/packet.
130 self.put(self.ss, self.es, self.out_ann, data)
132 def putb(self, data):
133 self.put(self.ss_block, self.es_block, self.out_ann, data)
135 def vendor_device(self):
136 dev = device_name[self.vendor].get(self.device_id, 'Unknown')
137 return '%s %s' % (self.chip['vendor'], dev)
139 def handle_wren(self, mosi, miso):
140 self.putx([Ann.WREN, ['Command: %s' % cmds[self.state][1]]])
143 def handle_wrdi(self, mosi, miso):
146 # TODO: Check/display device ID / name
147 def handle_rdid(self, mosi, miso):
148 if self.cmdstate == 1:
149 # Byte 1: Master sends command ID.
150 self.ss_block = self.ss
151 self.putx([Ann.RDID, ['Command: %s' % cmds[self.state][1]]])
152 elif self.cmdstate == 2:
153 # Byte 2: Slave sends the JEDEC manufacturer ID.
154 self.putx([Ann.RDID, ['Manufacturer ID: 0x%02x' % miso]])
155 elif self.cmdstate == 3:
156 # Byte 3: Slave sends the memory type (0x20 for this chip).
157 self.putx([Ann.RDID, ['Memory type: 0x%02x' % miso]])
158 elif self.cmdstate == 4:
159 # Byte 4: Slave sends the device ID.
160 self.device_id = miso
161 self.putx([Ann.RDID, ['Device ID: 0x%02x' % miso]])
163 if self.cmdstate == 4:
164 # TODO: Same device ID? Check!
165 d = 'Device: %s' % self.vendor_device()
166 self.put(self.ss_block, self.es, self.out_ann, [Ann.RDID, [d]])
171 def handle_rdsr(self, mosi, miso):
172 # Read status register: Master asserts CS#, sends RDSR command,
173 # reads status register byte. If CS# is kept asserted, the status
174 # register can be read continuously / multiple times in a row.
175 # When done, the master de-asserts CS# again.
176 if self.cmdstate == 1:
177 # Byte 1: Master sends command ID.
178 self.putx([Ann.RDSR, ['Command: %s' % cmds[self.state][1]]])
179 elif self.cmdstate >= 2:
180 # Bytes 2-x: Slave sends status register as long as master clocks.
181 self.putx([Ann.BIT, ['Status register: 0x%02x' % miso]])
182 self.putx([Ann.FIELD, [decode_status_reg(miso)]])
186 def handle_rdsr2(self, mosi, miso):
187 # Read status register 2: Master asserts CS#, sends RDSR2 command,
188 # reads status register 2 byte. If CS# is kept asserted, the status
189 # register 2 can be read continuously / multiple times in a row.
190 # When done, the master de-asserts CS# again.
191 if self.cmdstate == 1:
192 # Byte 1: Master sends command ID.
193 self.putx([Ann.RDSR2, ['Command: %s' % cmds[self.state][1]]])
194 elif self.cmdstate >= 2:
195 # Bytes 2-x: Slave sends status register 2 as long as master clocks.
196 self.putx([Ann.BIT, ['Status register 2: 0x%02x' % miso]])
197 self.putx([Ann.FIELD, [decode_status_reg(miso)]])
198 # TODO: Handle status register 2 correctly.
202 def handle_wrsr(self, mosi, miso):
203 # Write status register: Master asserts CS#, sends WRSR command,
204 # writes 1 or 2 status register byte(s).
205 # When done, the master de-asserts CS# again. If this doesn't happen
206 # the WRSR command will not be executed.
207 if self.cmdstate == 1:
208 # Byte 1: Master sends command ID.
209 self.putx([Ann.WRSR, ['Command: %s' % cmds[self.state][1]]])
210 elif self.cmdstate in (2, 3):
211 # Bytes 2 and/or 3: Master sends status register byte(s).
212 self.putx([Ann.BIT, ['Status register: 0x%02x' % miso]])
213 self.putx([Ann.FIELD, [decode_status_reg(miso)]])
214 # TODO: Handle status register 2 correctly.
218 def handle_read(self, mosi, miso):
219 # Read data bytes: Master asserts CS#, sends READ command, sends
220 # 3-byte address, reads >= 1 data bytes, de-asserts CS#.
221 if self.cmdstate == 1:
222 # Byte 1: Master sends command ID.
223 self.putx([Ann.READ, ['Command: %s' % cmds[self.state][1]]])
224 elif self.cmdstate in (2, 3, 4):
225 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
226 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
227 # self.putx([Ann.READ, ['Read address, byte %d: 0x%02x' % \
228 # (4 - self.cmdstate, mosi)]])
229 if self.cmdstate == 4:
230 self.putx([Ann.BIT, ['Read address: 0x%06x' % self.addr]])
232 elif self.cmdstate >= 5:
233 # Bytes 5-x: Master reads data bytes (until CS# de-asserted).
234 if self.cmdstate == 5:
235 self.ss_block = self.ss
236 self.on_end_transaction = lambda: self.output_data_block('Read')
237 self.data.append(miso)
241 def handle_fast_read(self, mosi, miso):
242 # Fast read: Master asserts CS#, sends FAST READ command, sends
243 # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#.
244 if self.cmdstate == 1:
245 # Byte 1: Master sends command ID.
246 self.putx([Ann.FAST_READ, ['Command: %s' % cmds[self.state][1]]])
247 elif self.cmdstate in (2, 3, 4):
248 # Bytes 2/3/4: Master sends read address (25bits, MSB-first).
249 self.putx([Ann.BIT, ['AD%d: 0x%02x' % (self.cmdstate - 1, mosi)]])
250 if self.cmdstate == 2:
251 self.ss_block = self.ss
252 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
253 elif self.cmdstate == 5:
254 self.putx([Ann.BIT, ['Dummy byte: 0x%02x' % mosi]])
255 self.es_block = self.es
256 self.putb([Ann.FAST_READ, ['Read address: 0x%06x' % self.addr]])
258 elif self.cmdstate >= 6:
259 # Bytes 6-x: Master reads data bytes (until CS# de-asserted).
260 if self.cmdstate == 6:
261 self.ss_block = self.ss
262 self.on_end_transaction = lambda: self.output_data_block('Read')
263 self.data.append(miso)
267 def handle_2read(self, mosi, miso):
268 # Fast read dual I/O: Same as fast read, but all data
269 # after the command is sent via two I/O pins.
270 # MOSI = SIO0 = even bits, MISO = SIO1 = odd bits.
271 # Recombine the bytes and pass them up to the handle_fast_read command.
272 if self.cmdstate == 1:
273 # Byte 1: Master sends command ID.
274 self.putx([Ann.READ2X, ['Command: %s' % cmds[self.state][1]]])
278 a, b = decode_dual_bytes(mosi, miso)
279 # Pass same byte in as both MISO & MOSI, parser state determines
280 # which one it cares about.
281 self.handle_fast_read(a, a)
282 self.handle_fast_read(b, b)
284 # TODO: Warn/abort if we don't see the necessary amount of bytes.
285 # TODO: Warn if WREN was not seen before.
286 def handle_se(self, mosi, miso):
287 if self.cmdstate == 1:
288 # Byte 1: Master sends command ID.
290 self.ss_block = self.ss
291 self.putx([Ann.SE, ['Command: %s' % cmds[self.state][1]]])
292 elif self.cmdstate in (2, 3, 4):
293 # Bytes 2/3/4: Master sends sector address (24bits, MSB-first).
294 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
295 # self.putx([Ann.SE, ['Sector address, byte %d: 0x%02x' % \
296 # (4 - self.cmdstate, mosi)]])
298 if self.cmdstate == 4:
299 d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
300 self.put(self.ss_block, self.es, self.out_ann, [Ann.BIT, [d]])
301 # TODO: Max. size depends on chip, check that too if possible.
302 if self.addr % 4096 != 0:
303 # Sector addresses must be 4K-aligned (same for all 3 chips).
304 d = 'Warning: Invalid sector address!'
305 self.put(self.ss_block, self.es, self.out_ann, [Ann.WARN, [d]])
310 def handle_be(self, mosi, miso):
313 def handle_ce(self, mosi, miso):
316 def handle_ce2(self, mosi, miso):
319 def handle_pp(self, mosi, miso):
320 # Page program: Master asserts CS#, sends PP command, sends 3-byte
321 # page address, sends >= 1 data bytes, de-asserts CS#.
322 if self.cmdstate == 1:
323 # Byte 1: Master sends command ID.
324 self.putx([Ann.PP, ['Command: %s' % cmds[self.state][1]]])
325 elif self.cmdstate in (2, 3, 4):
326 # Bytes 2/3/4: Master sends page address (24bits, MSB-first).
327 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
328 # self.putx([Ann.PP, ['Page address, byte %d: 0x%02x' % \
329 # (4 - self.cmdstate, mosi)]])
330 if self.cmdstate == 4:
331 self.putx([Ann.BIT, ['Page address: 0x%06x' % self.addr]])
333 elif self.cmdstate >= 5:
334 # Bytes 5-x: Master sends data bytes (until CS# de-asserted).
335 if self.cmdstate == 5:
336 self.ss_block = self.ss
337 self.on_end_transaction = lambda: self.output_data_block('Page data')
338 self.data.append(mosi)
342 def handle_cp(self, mosi, miso):
345 def handle_dp(self, mosi, miso):
348 def handle_rdp_res(self, mosi, miso):
349 if self.cmdstate == 1:
350 # Byte 1: Master sends command ID.
351 self.ss_block = self.ss
352 self.putx([Ann.RDP_RES, ['Command: %s' % cmds[self.state][1]]])
353 elif self.cmdstate in (2, 3, 4):
354 # Bytes 2/3/4: Master sends three dummy bytes.
355 self.putx([Ann.BIT, ['Dummy byte: %02x' % mosi]])
356 elif self.cmdstate == 5:
357 # Byte 5: Slave sends device ID.
358 self.device_id = miso
359 self.putx([Ann.BIT, ['Device: %s' % self.vendor_device()]])
364 def handle_rems(self, mosi, miso):
365 if self.cmdstate == 1:
366 # Byte 1: Master sends command ID.
367 self.ss_block = self.ss
368 self.putx([Ann.REMS, ['Command: %s' % cmds[self.state][1]]])
369 elif self.cmdstate in (2, 3):
370 # Bytes 2/3: Master sends two dummy bytes.
371 # TODO: Check dummy bytes? Check reply from device?
372 self.putx([Ann.BIT, ['Dummy byte: %s' % mosi]])
373 elif self.cmdstate == 4:
374 # Byte 4: Master sends 0x00 or 0x01.
375 # 0x00: Master wants manufacturer ID as first reply byte.
376 # 0x01: Master wants device ID as first reply byte.
377 self.manufacturer_id_first = True if (mosi == 0x00) else False
378 d = 'manufacturer' if (mosi == 0x00) else 'device'
379 self.putx([Ann.BIT, ['Master wants %s ID first' % d]])
380 elif self.cmdstate == 5:
381 # Byte 5: Slave sends manufacturer ID (or device ID).
383 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
384 self.putx([Ann.BIT, ['%s ID' % d]])
385 elif self.cmdstate == 6:
386 # Byte 6: Slave sends device ID (or manufacturer ID).
387 self.ids.append(miso)
388 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
389 self.putx([Ann.BIT, ['%s ID' % d]])
391 if self.cmdstate == 6:
392 id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
394 self.putx([Ann.BIT, ['Device: %s' % self.vendor_device()]])
399 def handle_rems2(self, mosi, miso):
402 def handle_enso(self, mosi, miso):
405 def handle_exso(self, mosi, miso):
408 def handle_rdscur(self, mosi, miso):
411 def handle_wrscur(self, mosi, miso):
414 def handle_esry(self, mosi, miso):
417 def handle_dsry(self, mosi, miso):
420 def output_data_block(self, label):
421 # Print accumulated block of data
422 # (called on CS# de-assert via self.on_end_transaction callback).
423 self.es_block = self.es # Ends on the CS# de-assert sample.
424 if self.options['format'] == 'hex':
425 s = ' '.join([('%02x' % b) for b in self.data])
427 s = ''.join(map(chr, self.data))
428 self.putb([Ann.FIELD, ['%s %d bytes: %s' % (label, len(self.data), s)]])
430 def decode(self, ss, es, data):
431 ptype, mosi, miso = data
433 self.ss, self.es = ss, es
435 if ptype == 'CS-CHANGE':
436 self.end_current_transaction()
441 # If we encountered a known chip command, enter the resp. state.
442 if self.state is None:
448 self.cmd_handlers[self.state](mosi, miso)
450 self.putx([Ann.BIT, ['Unknown command: 0x%02x' % mosi]])