2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
24 # Key: (CPOL, CPHA). Value: SPI mode.
25 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
26 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
37 class Decoder(srd.Decoder):
41 longname = 'Serial Peripheral Interface'
43 longdesc = '...longdesc...'
48 {'id': 'miso', 'name': 'MISO',
49 'desc': 'SPI MISO line (Master in, slave out)'},
50 {'id': 'mosi', 'name': 'MOSI',
51 'desc': 'SPI MOSI line (Master out, slave in)'},
52 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
53 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
55 optional_probes = [] # TODO
57 'cs_polarity': ['CS# polarity', 'active-low'],
58 'cpol': ['Clock polarity', 0],
59 'cpha': ['Clock phase', 0],
60 'bitorder': ['Bit order within the SPI data', 'msb-first'],
61 'wordsize': ['Word size of SPI data', 8], # 1-64?
64 ['Hex', 'SPI data bytes in hex format'],
72 self.bytesreceived = 0
74 self.cs_was_deasserted_during_data_word = 0
76 def start(self, metadata):
77 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
78 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
81 return 'SPI: %d bytes received' % self.bytesreceived
83 def decode(self, ss, es, data):
84 # TODO: Either MISO or MOSI could be optional. CS# is optional.
85 for (samplenum, (miso, mosi, sck, cs)) in data:
87 self.samplenum += 1 # FIXME
89 # Ignore sample if the clock pin hasn't changed.
90 if sck == self.oldsck:
95 # Sample data on rising/falling clock edge (depends on mode).
96 mode = spi_mode[self.options['cpol'], self.options['cpha']]
97 if mode == 0 and sck == 0: # Sample on rising clock edge
99 elif mode == 1 and sck == 1: # Sample on falling clock edge
101 elif mode == 2 and sck == 1: # Sample on falling clock edge
103 elif mode == 3 and sck == 0: # Sample on rising clock edge
106 # If this is the first bit, save its sample number.
107 if self.bitcount == 0:
108 self.start_sample = samplenum
109 active_low = (self.options['cs_polarity'] == 'active-low')
110 deasserted = cs if active_low else not cs
112 self.cs_was_deasserted_during_data_word = 1
114 ws = self.options['wordsize']
116 # Receive MOSI bit into our shift register.
117 if self.options['bitorder'] == 'msb-first':
118 self.mosidata |= mosi << (ws - 1 - self.bitcount)
120 self.mosidata |= mosi << self.bitcount
122 # Receive MISO bit into our shift register.
123 if self.options['bitorder'] == 'msb-first':
124 self.misodata |= miso << (ws - 1 - self.bitcount)
126 self.misodata |= miso << self.bitcount
130 # Continue to receive if not enough bits were received, yet.
131 if self.bitcount != ws:
134 self.put(self.start_sample, self.samplenum, self.out_proto,
135 ['data', self.mosidata, self.misodata])
136 self.put(self.start_sample, self.samplenum, self.out_ann,
137 [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
140 if self.cs_was_deasserted_during_data_word:
141 self.put(self.start_sample, self.samplenum, self.out_ann,
142 [ANN_HEX, ['WARNING: CS# was deasserted during this '
145 # Reset decoder state.
150 # Keep stats for summary.
151 self.bytesreceived += 1