2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # SPI protocol decoder
24 import sigrokdecode as srd
26 # Key: (CPOL, CPHA). Value: SPI mode.
27 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
28 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
36 class Decoder(srd.Decoder):
40 longname = 'Serial Peripheral Interface'
41 desc = 'Full-duplex, synchronous, serial bus.'
46 {'id': 'miso', 'name': 'MISO',
47 'desc': 'SPI MISO line (Master in, slave out)'},
48 {'id': 'mosi', 'name': 'MOSI',
49 'desc': 'SPI MOSI line (Master out, slave in)'},
50 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
53 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
56 'cs_polarity': ['CS# polarity', 'active-low'],
57 'cpol': ['Clock polarity', 0],
58 'cpha': ['Clock phase', 0],
59 'bitorder': ['Bit order within the SPI data', 'msb-first'],
60 'wordsize': ['Word size of SPI data', 8], # 1-64?
61 'format': ['Data format', 'hex'],
64 ['MISO/MOSI data', 'MISO/MOSI SPI data'],
65 ['MISO data', 'MISO SPI data'],
66 ['MOSI data', 'MOSI SPI data'],
67 ['Warnings', 'Human-readable warnings'],
75 self.bytesreceived = 0
78 self.cs_was_deasserted_during_data_word = 0
83 def start(self, metadata):
84 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
85 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
88 return 'SPI: %d bytes received' % self.bytesreceived
90 def putpw(self, data):
91 self.put(self.startsample, self.samplenum, self.out_proto, data)
94 self.put(self.startsample, self.samplenum, self.out_ann, data)
96 def handle_bit(self, miso, mosi, sck, cs):
97 # If this is the first bit, save its sample number.
98 if self.bitcount == 0:
99 self.startsample = self.samplenum
101 active_low = (self.options['cs_polarity'] == 'active-low')
102 deasserted = cs if active_low else not cs
104 self.cs_was_deasserted_during_data_word = 1
106 ws = self.options['wordsize']
108 # Receive MOSI bit into our shift register.
109 if self.options['bitorder'] == 'msb-first':
110 self.mosidata |= mosi << (ws - 1 - self.bitcount)
112 self.mosidata |= mosi << self.bitcount
114 # Receive MISO bit into our shift register.
115 if self.options['bitorder'] == 'msb-first':
116 self.misodata |= miso << (ws - 1 - self.bitcount)
118 self.misodata |= miso << self.bitcount
122 # Continue to receive if not enough bits were received, yet.
123 if self.bitcount != ws:
126 self.putpw(['DATA', self.mosidata, self.misodata])
127 self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
128 self.putw([1, ['%02X' % self.misodata]])
129 self.putw([2, ['%02X' % self.mosidata]])
131 if self.cs_was_deasserted_during_data_word:
132 self.putw([3, ['CS# was deasserted during this data word!']])
134 # Reset decoder state.
135 self.mosidata = self.misodata = self.bitcount = 0
137 # Keep stats for summary.
138 self.bytesreceived += 1
140 def find_clk_edge(self, miso, mosi, sck, cs):
141 if self.have_cs and self.oldcs != cs:
142 # Send all CS# pin value changes.
143 self.put(self.samplenum, self.samplenum, self.out_proto,
144 ['CS-CHANGE', self.oldcs, cs])
146 # Reset decoder state when CS# changes (and the CS# pin is used).
147 self.mosidata = self.misodata = self.bitcount= 0
149 # Ignore sample if the clock pin hasn't changed.
150 if sck == self.oldsck:
155 # Sample data on rising/falling clock edge (depends on mode).
156 mode = spi_mode[self.options['cpol'], self.options['cpha']]
157 if mode == 0 and sck == 0: # Sample on rising clock edge
159 elif mode == 1 and sck == 1: # Sample on falling clock edge
161 elif mode == 2 and sck == 1: # Sample on falling clock edge
163 elif mode == 3 and sck == 0: # Sample on rising clock edge
166 # Found the correct clock edge, now get the SPI bit(s).
167 self.handle_bit(miso, mosi, sck, cs)
169 def decode(self, ss, es, data):
170 # TODO: Either MISO or MOSI could be optional. CS# is optional.
171 for (self.samplenum, pins) in data:
173 # Ignore identical samples early on (for performance reasons).
174 if self.oldpins == pins:
176 self.oldpins, (miso, mosi, sck, cs) = pins, pins
177 self.have_cs = (cs in (0, 1))
180 if self.state == 'IDLE':
181 self.find_clk_edge(miso, mosi, sck, cs)
183 raise Exception('Invalid state: %s' % self.state)