2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
28 [<cmd>, <data1>, <data2>]
31 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
32 The data is _usually_ 8 bits (but can also be fewer or more bits).
33 Both data items are Python numbers (not strings), or None if the respective
34 probe was not supplied.
35 - 'BITS': <data1>/<data2> contain a list of bit values in this MISO/MOSI data
36 item, and for each of those also their respective start-/endsample numbers.
37 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
38 Both data items are Python numbers (0/1), not strings.
43 ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
44 [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]],
45 [[0, 80, 82], [0, 83, 84], [1, 85, 86], [1, 87, 88],
46 [1, 89, 90], [0, 91, 92], [1, 93, 94], [0, 95, 96]]]
53 # Key: (CPOL, CPHA). Value: SPI mode.
54 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
55 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
63 class Decoder(srd.Decoder):
67 longname = 'Serial Peripheral Interface'
68 desc = 'Full-duplex, synchronous, serial bus.'
73 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
76 {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
77 {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
78 {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
81 'cs_polarity': ['CS# polarity', 'active-low'],
82 'cpol': ['Clock polarity', 0],
83 'cpha': ['Clock phase', 0],
84 'bitorder': ['Bit order within the SPI data', 'msb-first'],
85 'wordsize': ['Word size of SPI data', 8], # 1-64?
86 'format': ['Data format', 'hex'],
89 ['miso-data', 'MISO data'],
90 ['mosi-data', 'MOSI data'],
91 ['miso-bits', 'MISO bits'],
92 ['mosi-bits', 'MOSI bits'],
93 ['warnings', 'Human-readable warnings'],
96 ('miso-data', 'MISO data', (0,)),
97 ('miso-bits', 'MISO bits', (2,)),
98 ('mosi-data', 'MOSI data', (1,)),
99 ('mosi-bits', 'MOSI bits', (3,)),
100 ('other', 'Other', (4,)),
104 self.samplerate = None
111 self.startsample = -1
113 self.cs_was_deasserted_during_data_word = 0
117 self.have_miso = None
118 self.have_mosi = None
121 def metadata(self, key, value):
122 if key == srd.SRD_CONF_SAMPLERATE:
123 self.samplerate = value
126 self.out_python = self.register(srd.OUTPUT_PYTHON)
127 self.out_ann = self.register(srd.OUTPUT_ANN)
128 self.out_bitrate = self.register(srd.OUTPUT_META,
129 meta=(int, 'Bitrate', 'Bitrate during transfers'))
131 def putpw(self, data):
132 self.put(self.startsample, self.samplenum, self.out_python, data)
134 def putw(self, data):
135 self.put(self.startsample, self.samplenum, self.out_ann, data)
137 def putmisobit(self, i, data):
138 self.put(self.misobits[i][1], self.misobits[i][2], self.out_ann, data)
140 def putmosibit(self, i, data):
141 self.put(self.mosibits[i][1], self.mosibits[i][2], self.out_ann, data)
143 def handle_bit(self, miso, mosi, clk, cs):
144 # If this is the first bit of a dataword, save its sample number.
145 if self.bitcount == 0:
146 self.startsample = self.samplenum
148 active_low = (self.options['cs_polarity'] == 'active-low')
149 deasserted = cs if active_low else not cs
151 self.cs_was_deasserted_during_data_word = 1
153 ws = self.options['wordsize']
155 # Receive MOSI bit into our shift register.
157 if self.options['bitorder'] == 'msb-first':
158 self.mosidata |= mosi << (ws - 1 - self.bitcount)
160 self.mosidata |= mosi << self.bitcount
162 # Receive MISO bit into our shift register.
164 if self.options['bitorder'] == 'msb-first':
165 self.misodata |= miso << (ws - 1 - self.bitcount)
167 self.misodata |= miso << self.bitcount
170 self.misobits.append([miso, self.samplenum, -1])
172 self.mosibits.append([mosi, self.samplenum, -1])
173 if self.bitcount != 0:
175 self.misobits[self.bitcount - 1][2] = self.samplenum
176 self.putmisobit(self.bitcount - 1, [3, ['%d' % miso]])
178 self.mosibits[self.bitcount - 1][2] = self.samplenum
179 self.putmosibit(self.bitcount - 1, [2, ['%d' % mosi]])
183 # Continue to receive if not enough bits were received, yet.
184 if self.bitcount != ws:
187 si = self.mosidata if self.have_mosi else None
188 so = self.misodata if self.have_miso else None
189 si_bits = self.mosibits if self.have_mosi else None
190 so_bits = self.misobits if self.have_miso else None
192 # Pass MOSI and MISO to the next PD up the stack.
193 self.putpw(['DATA', si, so])
194 self.putpw(['BITS', si_bits, so_bits])
198 self.putw([0, ['%02X' % self.misodata]])
200 self.putw([1, ['%02X' % self.mosidata]])
203 elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
204 bitrate = int(1 / elapsed * self.options['wordsize'])
205 self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
207 if self.have_cs and self.cs_was_deasserted_during_data_word:
208 self.putw([4, ['CS# was deasserted during this data word!']])
210 # Reset decoder state.
211 self.misodata = 0 if self.have_miso else None
212 self.mosidata = 0 if self.have_mosi else None
213 self.misobits = [] if self.have_miso else None
214 self.mosibits = [] if self.have_mosi else None
217 def find_clk_edge(self, miso, mosi, clk, cs):
218 if self.have_cs and self.oldcs != cs:
219 # Send all CS# pin value changes.
220 self.put(self.samplenum, self.samplenum, self.out_python,
221 ['CS-CHANGE', self.oldcs, cs])
223 # Reset decoder state when CS# changes (and the CS# pin is used).
224 self.misodata = 0 if self.have_miso else None
225 self.mosidata = 0 if self.have_mosi else None
228 # Ignore sample if the clock pin hasn't changed.
229 if clk == self.oldclk:
234 # Sample data on rising/falling clock edge (depends on mode).
235 mode = spi_mode[self.options['cpol'], self.options['cpha']]
236 if mode == 0 and clk == 0: # Sample on rising clock edge
238 elif mode == 1 and clk == 1: # Sample on falling clock edge
240 elif mode == 2 and clk == 1: # Sample on falling clock edge
242 elif mode == 3 and clk == 0: # Sample on rising clock edge
245 # Found the correct clock edge, now get the SPI bit(s).
246 self.handle_bit(miso, mosi, clk, cs)
248 def decode(self, ss, es, data):
249 if self.samplerate is None:
250 raise Exception("Cannot decode without samplerate.")
251 # Either MISO or MOSI can be omitted (but not both). CS# is optional.
252 for (self.samplenum, pins) in data:
254 # Ignore identical samples early on (for performance reasons).
255 if self.oldpins == pins:
257 self.oldpins, (clk, miso, mosi, cs) = pins, pins
258 self.have_miso = (miso in (0, 1))
259 self.have_mosi = (mosi in (0, 1))
260 self.have_cs = (cs in (0, 1))
263 if self.state == 'IDLE':
264 self.find_clk_edge(miso, mosi, clk, cs)
266 raise Exception('Invalid state: %s' % self.state)