2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
28 [<cmd>, <data1>, <data2>]
31 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
32 The data is _usually_ 8 bits (but can also be fewer or more bits).
33 Both data items are Python numbers (not strings), or None if the respective
34 probe was not supplied.
35 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
36 Both data items are Python numbers (0/1), not strings.
47 # Key: (CPOL, CPHA). Value: SPI mode.
48 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
49 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
57 class Decoder(srd.Decoder):
61 longname = 'Serial Peripheral Interface'
62 desc = 'Full-duplex, synchronous, serial bus.'
67 {'id': 'clk', 'name': 'CLK', 'desc': 'SPI clock line'},
70 {'id': 'miso', 'name': 'MISO',
71 'desc': 'SPI MISO line (master in, slave out)'},
72 {'id': 'mosi', 'name': 'MOSI',
73 'desc': 'SPI MOSI line (master out, slave in)'},
74 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
77 'cs_polarity': ['CS# polarity', 'active-low'],
78 'cpol': ['Clock polarity', 0],
79 'cpha': ['Clock phase', 0],
80 'bitorder': ['Bit order within the SPI data', 'msb-first'],
81 'wordsize': ['Word size of SPI data', 8], # 1-64?
82 'format': ['Data format', 'hex'],
85 ['miso-data', 'MISO SPI data'],
86 ['mosi-data', 'MOSI SPI data'],
87 ['warnings', 'Human-readable warnings'],
90 ('miso', 'MISO', (0,)),
91 ('mosi', 'MOSI', (1,)),
92 ('other', 'Other', (2,)),
96 self.samplerate = None
101 self.startsample = -1
103 self.cs_was_deasserted_during_data_word = 0
107 self.have_miso = None
108 self.have_mosi = None
111 def metadata(self, key, value):
112 if key == srd.SRD_CONF_SAMPLERATE:
113 self.samplerate = value
116 self.out_python = self.register(srd.OUTPUT_PYTHON)
117 self.out_ann = self.register(srd.OUTPUT_ANN)
118 self.out_bitrate = self.register(srd.OUTPUT_META,
119 meta=(int, 'Bitrate', 'Bitrate during transfers'))
121 def putpw(self, data):
122 self.put(self.startsample, self.samplenum, self.out_python, data)
124 def putw(self, data):
125 self.put(self.startsample, self.samplenum, self.out_ann, data)
127 def handle_bit(self, miso, mosi, clk, cs):
128 # If this is the first bit, save its sample number.
129 if self.bitcount == 0:
130 self.startsample = self.samplenum
132 active_low = (self.options['cs_polarity'] == 'active-low')
133 deasserted = cs if active_low else not cs
135 self.cs_was_deasserted_during_data_word = 1
137 ws = self.options['wordsize']
139 # Receive MOSI bit into our shift register.
141 if self.options['bitorder'] == 'msb-first':
142 self.mosidata |= mosi << (ws - 1 - self.bitcount)
144 self.mosidata |= mosi << self.bitcount
146 # Receive MISO bit into our shift register.
148 if self.options['bitorder'] == 'msb-first':
149 self.misodata |= miso << (ws - 1 - self.bitcount)
151 self.misodata |= miso << self.bitcount
155 # Continue to receive if not enough bits were received, yet.
156 if self.bitcount != ws:
159 si = self.mosidata if self.have_mosi else None
160 so = self.misodata if self.have_miso else None
162 # Pass MOSI and MISO to the next PD up the stack.
163 self.putpw(['DATA', si, so])
167 self.putw([0, ['%02X' % self.misodata]])
169 self.putw([1, ['%02X' % self.mosidata]])
172 elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
173 bitrate = int(1 / elapsed * self.options['wordsize'])
174 self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
176 if self.have_cs and self.cs_was_deasserted_during_data_word:
177 self.putw([2, ['CS# was deasserted during this data word!']])
179 # Reset decoder state.
180 self.misodata = 0 if self.have_miso else None
181 self.mosidata = 0 if self.have_mosi else None
184 def find_clk_edge(self, miso, mosi, clk, cs):
185 if self.have_cs and self.oldcs != cs:
186 # Send all CS# pin value changes.
187 self.put(self.samplenum, self.samplenum, self.out_python,
188 ['CS-CHANGE', self.oldcs, cs])
190 # Reset decoder state when CS# changes (and the CS# pin is used).
191 self.misodata = 0 if self.have_miso else None
192 self.mosidata = 0 if self.have_mosi else None
195 # Ignore sample if the clock pin hasn't changed.
196 if clk == self.oldclk:
201 # Sample data on rising/falling clock edge (depends on mode).
202 mode = spi_mode[self.options['cpol'], self.options['cpha']]
203 if mode == 0 and clk == 0: # Sample on rising clock edge
205 elif mode == 1 and clk == 1: # Sample on falling clock edge
207 elif mode == 2 and clk == 1: # Sample on falling clock edge
209 elif mode == 3 and clk == 0: # Sample on rising clock edge
212 # Found the correct clock edge, now get the SPI bit(s).
213 self.handle_bit(miso, mosi, clk, cs)
215 def decode(self, ss, es, data):
216 if self.samplerate is None:
217 raise Exception("Cannot decode without samplerate.")
218 # Either MISO or MOSI can be omitted (but not both). CS# is optional.
219 for (self.samplenum, pins) in data:
221 # Ignore identical samples early on (for performance reasons).
222 if self.oldpins == pins:
224 self.oldpins, (clk, miso, mosi, cs) = pins, pins
225 self.have_miso = (miso in (0, 1))
226 self.have_mosi = (mosi in (0, 1))
227 self.have_cs = (cs in (0, 1))
230 if self.state == 'IDLE':
231 self.find_clk_edge(miso, mosi, clk, cs)
233 raise Exception('Invalid state: %s' % self.state)