2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
27 class Decoder(srd.Decoder):
30 longname = 'Serial Peripheral Interface (SPI) bus'
32 longdesc = '...longdesc...'
33 author = 'Gareth McMullin'
34 email = 'gareth@blacksphere.co.nz'
39 {'id': 'mosi', 'name': 'MOSI',
40 'desc': 'SPI MOSI line (Master out, slave in)'},
41 {'id': 'miso', 'name': 'MISO',
42 'desc': 'SPI MISO line (Master in, slave out)'},
43 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
44 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
48 ['Hex', 'SPI data bytes in hex format'],
56 self.bytesreceived = 0
59 def start(self, metadata):
60 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
61 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
64 return 'SPI: %d bytes received' % self.bytesreceived
66 def decode(self, ss, es, data):
67 # HACK! At the moment the number of probes is not handled correctly.
68 # E.g. if an input file (-i foo.sr) has more than two probes enabled.
69 # for (samplenum, (mosi, sck, x, y, z, a)) in data:
70 # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
71 for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
73 self.samplenum += 1 # FIXME
75 # Sample data on rising SCK edges.
76 if sck == self.oldsck:
82 # If this is the first bit, save its sample number.
83 if self.bitcount == 0:
84 self.start_sample = samplenum
86 # Receive bit into our shift register.
88 self.mosidata |= 1 << (7 - self.bitcount)
90 self.misodata |= 1 << (7 - self.bitcount)
94 # Continue to receive if not a byte yet.
95 if self.bitcount != 8:
98 self.put(self.start_sample, self.samplenum, self.out_proto,
99 ['data', self.mosidata, self.misodata])
100 self.put(self.start_sample, self.samplenum, self.out_ann,
101 [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
104 # Reset decoder state.
109 # Keep stats for summary.
110 self.bytesreceived += 1