2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # Return the specified BCD number (max. 8 bits) as integer.
25 return (b & 0x0f) + ((b >> 4) * 10)
27 class Decoder(srd.Decoder):
31 longname = 'Epson RTC-8564 JE/NB'
32 desc = 'Realtime clock module protocol.'
38 {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
39 {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
40 {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
44 [['reg-0x%02x' % i, 'Register 0x%02x' % i] for i in range(8 + 1)] + [
45 ['read', 'Read date/time'],
46 ['write', 'Write date/time'],
47 ['bit-reserved', 'Reserved bit'],
49 ['bit-century', 'Century bit'],
50 ['reg-read', 'Register read'],
51 ['reg-write', 'Register write'],
54 ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
55 ('regs', 'Register access', (14, 15)),
56 ('date-time', 'Date/time', (9, 10)),
59 def __init__(self, **kwargs):
71 # self.out_python = self.register(srd.OUTPUT_PYTHON)
72 self.out_ann = self.register(srd.OUTPUT_ANN)
75 self.put(self.ss, self.es, self.out_ann, data)
77 def putd(self, bit1, bit2, data):
78 self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
81 self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
82 [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
84 def handle_reg_0x00(self, b): # Control register 1
87 def handle_reg_0x01(self, b): # Control register 2
88 ti_tp = 1 if (b & (1 << 4)) else 0
89 af = 1 if (b & (1 << 3)) else 0
90 tf = 1 if (b & (1 << 2)) else 0
91 aie = 1 if (b & (1 << 1)) else 0
92 tie = 1 if (b & (1 << 0)) else 0
96 s = 'repeated' if ti_tp else 'single-shot'
97 ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
98 'events\n' % (ti_tp, s)
99 s = '' if af else 'no '
100 ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
101 s = '' if tf else 'no '
102 ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
103 s = 'enabled' if aie else 'prohibited'
104 ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
105 'occurs\n' % (aie, s)
106 s = 'enabled' if tie else 'prohibited'
107 ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
108 'event occurs\n' % (tie, s)
110 self.putx([1, [ann]])
112 def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
113 vl = 1 if (b & (1 << 7)) else 0
114 self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
115 'VL: %d' % vl, 'VL']])
116 s = self.seconds = bcd2int(b & 0x7f)
117 self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
119 def handle_reg_0x03(self, b): # Minutes
121 m = self.minutes = bcd2int(b & 0x7f)
122 self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
124 def handle_reg_0x04(self, b): # Hours
127 h = self.hours = bcd2int(b & 0x3f)
128 self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])
130 def handle_reg_0x05(self, b): # Days
133 d = self.days = bcd2int(b & 0x3f)
134 self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])
136 def handle_reg_0x06(self, b): # Weekdays
137 for i in (7, 6, 5, 4, 3):
139 w = self.weekdays = bcd2int(b & 0x07)
140 self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])
142 def handle_reg_0x07(self, b): # Months / century bit
143 c = 1 if (b & (1 << 7)) else 0
144 self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
145 'Cent: %d' % c, 'C: %d' % c, 'C']])
148 m = self.months = bcd2int(b & 0x1f)
149 self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
151 def handle_reg_0x08(self, b): # Years
152 y = self.years = bcd2int(b & 0xff)
153 self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
155 def handle_reg_0x09(self, b): # Alarm, minute
158 def handle_reg_0x0a(self, b): # Alarm, hour
161 def handle_reg_0x0b(self, b): # Alarm, day
164 def handle_reg_0x0c(self, b): # Alarm, weekday
167 def handle_reg_0x0d(self, b): # CLKOUT output
170 def handle_reg_0x0e(self, b): # Timer setting
173 def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
176 def decode(self, ss, es, data):
179 # Collect the 'BITS' packet, then return. The next packet is
180 # guaranteed to belong to these bits we just stored.
185 # Store the start/end samples of this I²C packet.
186 self.ss, self.es = ss, es
189 if self.state == 'IDLE':
190 # Wait for an I²C START condition.
193 self.state = 'GET SLAVE ADDR'
194 self.block_start_sample = ss
195 elif self.state == 'GET SLAVE ADDR':
196 # Wait for an address write operation.
197 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
198 if cmd != 'ADDRESS WRITE':
200 self.state = 'GET REG ADDR'
201 elif self.state == 'GET REG ADDR':
202 # Wait for a data write (master selects the slave register).
203 if cmd != 'DATA WRITE':
206 self.state = 'WRITE RTC REGS'
207 elif self.state == 'WRITE RTC REGS':
208 # If we see a Repeated Start here, it's probably an RTC read.
209 if cmd == 'START REPEAT':
210 self.state = 'READ RTC REGS'
212 # Otherwise: Get data bytes until a STOP condition occurs.
213 if cmd == 'DATA WRITE':
214 r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
215 self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
216 'WR %s' % s, 'WR', 'W']])
217 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
220 # TODO: Check for NACK!
222 # TODO: Handle read/write of only parts of these items.
223 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
224 self.years, self.hours, self.minutes, self.seconds)
225 self.put(self.block_start_sample, es, self.out_ann,
226 [9, ['Write date/time: %s' % d, 'Write: %s' % d,
231 elif self.state == 'READ RTC REGS':
232 # Wait for an address read operation.
233 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
234 if cmd == 'ADDRESS READ':
235 self.state = 'READ RTC REGS2'
239 elif self.state == 'READ RTC REGS2':
240 if cmd == 'DATA READ':
241 r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
242 self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
243 'RR %s' % s, 'RR', 'R']])
244 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
247 # TODO: Check for NACK!
249 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
250 self.years, self.hours, self.minutes, self.seconds)
251 self.put(self.block_start_sample, es, self.out_ann,
252 [10, ['Read date/time: %s' % d, 'Read: %s' % d,
258 raise Exception('Invalid state: %s' % self.state)