2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # Return the specified BCD number (max. 8 bits) as integer.
25 return (b & 0x0f) + ((b >> 4) * 10)
27 class Decoder(srd.Decoder):
31 longname = 'Epson RTC-8564 JE/NB'
32 desc = 'Realtime clock module protocol.'
38 {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
39 {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
40 {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
44 ['reg-0x00', 'Register 0x00'],
45 ['reg-0x01', 'Register 0x01'],
46 ['reg-0x02', 'Register 0x02'],
47 ['reg-0x03', 'Register 0x03'],
48 ['reg-0x04', 'Register 0x04'],
49 ['reg-0x05', 'Register 0x05'],
50 ['reg-0x06', 'Register 0x06'],
51 ['reg-0x07', 'Register 0x07'],
52 ['reg-0x08', 'Register 0x08'],
53 ['read', 'Read date/time'],
54 ['write', 'Write date/time'],
55 ['bit-reserved', 'Reserved bit'],
57 ['bit-century', 'Century bit'],
58 ['reg-read', 'Register read'],
59 ['reg-write', 'Register write'],
62 ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
63 ('regs', 'Register access', (14, 15)),
64 ('date-time', 'Date/time', (9, 10)),
67 def __init__(self, **kwargs):
79 # self.out_python = self.register(srd.OUTPUT_PYTHON)
80 self.out_ann = self.register(srd.OUTPUT_ANN)
83 self.put(self.ss, self.es, self.out_ann, data)
85 def putd(self, bit1, bit2, data):
86 self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
89 self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
90 [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
92 def handle_reg_0x00(self, b): # Control register 1
95 def handle_reg_0x01(self, b): # Control register 2
96 ti_tp = 1 if (b & (1 << 4)) else 0
97 af = 1 if (b & (1 << 3)) else 0
98 tf = 1 if (b & (1 << 2)) else 0
99 aie = 1 if (b & (1 << 1)) else 0
100 tie = 1 if (b & (1 << 0)) else 0
104 s = 'repeated' if ti_tp else 'single-shot'
105 ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
106 'events\n' % (ti_tp, s)
107 s = '' if af else 'no '
108 ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
109 s = '' if tf else 'no '
110 ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
111 s = 'enabled' if aie else 'prohibited'
112 ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
113 'occurs\n' % (aie, s)
114 s = 'enabled' if tie else 'prohibited'
115 ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
116 'event occurs\n' % (tie, s)
118 self.putx([1, [ann]])
120 def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
121 vl = 1 if (b & (1 << 7)) else 0
122 self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
124 s = self.seconds = bcd2int(b & 0x7f)
125 self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s]])
127 def handle_reg_0x03(self, b): # Minutes
129 m = self.minutes = bcd2int(b & 0x7f)
130 self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m]])
132 def handle_reg_0x04(self, b): # Hours
135 h = self.hours = bcd2int(b & 0x3f)
136 self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h]])
138 def handle_reg_0x05(self, b): # Days
141 d = self.days = bcd2int(b & 0x3f)
142 self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d]])
144 def handle_reg_0x06(self, b): # Weekdays
145 for i in (7, 6, 5, 4, 3):
147 w = self.weekdays = bcd2int(b & 0x07)
148 self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w]])
150 def handle_reg_0x07(self, b): # Months / century bit
151 c = 1 if (b & (1 << 7)) else 0
152 self.putd(7, 7, [13, ['Century: %d' % c, 'Cent: %d' % c, 'C: %d' % c]])
155 m = self.months = bcd2int(b & 0x1f)
156 self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m]])
158 def handle_reg_0x08(self, b): # Years
159 y = self.years = bcd2int(b & 0xff)
160 self.putx([8, ['Year: %d' % y, 'Y: %d' % y]])
162 def handle_reg_0x09(self, b): # Alarm, minute
165 def handle_reg_0x0a(self, b): # Alarm, hour
168 def handle_reg_0x0b(self, b): # Alarm, day
171 def handle_reg_0x0c(self, b): # Alarm, weekday
174 def handle_reg_0x0d(self, b): # CLKOUT output
177 def handle_reg_0x0e(self, b): # Timer setting
180 def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
183 def decode(self, ss, es, data):
186 # Collect the 'BITS' packet, then return. The next packet is
187 # guaranteed to belong to these bits we just stored.
192 # Store the start/end samples of this I²C packet.
193 self.ss, self.es = ss, es
196 if self.state == 'IDLE':
197 # Wait for an I²C START condition.
200 self.state = 'GET SLAVE ADDR'
201 self.block_start_sample = ss
202 elif self.state == 'GET SLAVE ADDR':
203 # Wait for an address write operation.
204 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
205 if cmd != 'ADDRESS WRITE':
207 self.state = 'GET REG ADDR'
208 elif self.state == 'GET REG ADDR':
209 # Wait for a data write (master selects the slave register).
210 if cmd != 'DATA WRITE':
213 self.state = 'WRITE RTC REGS'
214 elif self.state == 'WRITE RTC REGS':
215 # If we see a Repeated Start here, it's probably an RTC read.
216 if cmd == 'START REPEAT':
217 self.state = 'READ RTC REGS'
219 # Otherwise: Get data bytes until a STOP condition occurs.
220 if cmd == 'DATA WRITE':
221 r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
222 self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
223 'WR %s' % s, 'WR', 'W']])
224 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
227 # TODO: Check for NACK!
229 # TODO: Handle read/write of only parts of these items.
230 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
231 self.years, self.hours, self.minutes, self.seconds)
232 self.put(self.block_start_sample, es, self.out_ann,
233 [9, ['Write date/time: %s' % d, 'Write: %s' % d,
238 elif self.state == 'READ RTC REGS':
239 # Wait for an address read operation.
240 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
241 if cmd == 'ADDRESS READ':
242 self.state = 'READ RTC REGS2'
246 elif self.state == 'READ RTC REGS2':
247 if cmd == 'DATA READ':
248 r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
249 self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
250 'RR %s' % s, 'RR', 'R']])
251 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
254 # TODO: Check for NACK!
256 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
257 self.years, self.hours, self.minutes, self.seconds)
258 self.put(self.block_start_sample, es, self.out_ann,
259 [10, ['Read date/time: %s' % d, 'Read: %s' % d,
265 raise Exception('Invalid state: %s' % self.state)