2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # 1-Wire protocol decoder
23 import sigrokdecode as srd
25 # Annotation feed formats
32 class Decoder(srd.Decoder):
37 desc = '1-Wire bus and MicroLan'
42 {'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
45 {'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
48 'overdrive': ['Overdrive', 0],
51 ['ASCII', 'Data bytes as ASCII characters'],
52 ['Decimal', 'Databytes as decimal, integer values'],
53 ['Hex', 'Data bytes in hex format'],
54 ['Octal', 'Data bytes as octal numbers'],
55 ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
59 self.put(self.startsample, self.samplenum - 1, self.out_ann, data)
61 def __init__(self, **kwargs):
64 # Link layer variables
65 self.lnk_state = 'WAIT FOR EVENT'
66 self.lnk_event = 'NONE'
71 # Network layer variables
72 self.net_state = 'WAIT FOR EVENT'
73 self.net_event = 'NONE'
75 # Transport layer variables
76 self.trn_state = 'WAIT FOR EVENT'
77 self.trn_event = 'NONE'
84 def start(self, metadata):
85 self.samplerate = metadata['samplerate']
86 self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
87 self.out_ann = self.add(srd.OUTPUT_ANN, 'onewire')
89 # The width of the 1-Wire time base (30us) in number of samples.
90 # TODO: optimize this value
91 self.time_base = float(self.samplerate) / float(0.000030)
96 def get_data_sample(self, owr):
97 # Skip samples until we're in the middle of the start bit.
98 if not self.reached_data_sample():
101 self.data_sample = owr
103 self.cur_data_bit = 0
105 self.startsample = -1
107 self.state = 'GET DATA BITS'
109 self.put(self.cycle_start, self.samplenum, self.out_proto,
110 ['STARTBIT', self.startbit])
111 self.put(self.cycle_start, self.samplenum, self.out_ann,
112 [ANN_ASCII, ['Start bit', 'Start', 'S']])
114 def get_data_bits(self, owr):
115 # Skip samples until we're in the middle of the desired data bit.
116 if not self.reached_bit(self.cur_data_bit + 1):
119 # Save the sample number where the data byte starts.
120 if self.startsample == -1:
121 self.startsample = self.samplenum
123 # Get the next data bit in LSB-first or MSB-first fashion.
124 if self.options['bit_order'] == 'lsb-first':
127 (owr << (self.options['num_data_bits'] - 1))
128 elif self.options['bit_order'] == 'msb-first':
130 self.databyte |= (owr << 0)
132 raise Exception('Invalid bit order value: %s',
133 self.options['bit_order'])
135 # Return here, unless we already received all data bits.
137 if self.cur_data_bit < self.options['num_data_bits'] - 1:
138 self.cur_data_bit += 1
141 self.state = 'GET PARITY BIT'
143 self.put(self.startsample, self.samplenum - 1, self.out_proto,
144 ['DATA', self.databyte])
146 self.putx([ANN_ASCII, [chr(self.databyte)]])
147 self.putx([ANN_DEC, [str(self.databyte)]])
148 self.putx([ANN_HEX, [hex(self.databyte),
149 hex(self.databyte)[2:]]])
150 self.putx([ANN_OCT, [oct(self.databyte),
151 oct(self.databyte)[2:]]])
152 self.putx([ANN_BITS, [bin(self.databyte),
153 bin(self.databyte)[2:]]])
155 def decode(self, ss, es, data):
156 for (self.samplenum, owr) in data:
158 # First sample: Save OWR value.
159 if self.oldbit == None:
164 if self.lnk_state == 'WAIT FOR FALLING EDGE':
165 # The start of a cycle is a falling edge.
166 if (old_owr == 1 and owr == 0):
167 # Save the sample number where the start bit begins.
168 self.lnk_start = self.samplenum
169 # Go to waiting for sample time
170 self.lnk_state = 'WAIT FOR SAMPLE'
171 elif self.lnk_state == 'WAIT FOR SAMPLE':
172 # Data should be sample one 'time unit' after a falling edge
173 if (self.samplenum == self.lnk_start + self.time_base):
174 self.lnk_bit = owr & 0x1
175 self.lnk_cnt = self.lnk_cnt + 1
176 self.lnk_byte = (self.lnk_byte << 1) & self.lnk_bit
177 self.lnk_state = 'WAIT FOR RISING EDGE'
178 elif self.lnk_state == 'WAIT FOR RISING EDGE':
179 # The end of a cycle is a rising edge.
180 if (old_owr == 0 and owr == 1):
181 # Data bit cycle length should be between 2*T and
182 if (self.samplenum < self.lnk_start + 2*self.time_base):
183 if (self.lnk_cnt == 8)
184 self.put(self.startsample, self.samplenum - 1, self.out_proto, ['BYTE', self.lnk_byte])
186 if (self.samplenum == self.lnk_start + 8*self.time_base):
187 self.put(self.startsample, self.samplenum - 1, self.out_proto, ['RESET'])
189 # Go to waiting for sample time
190 self.lnk_state = 'WAIT FOR SAMPLE'
192 elif self.state_lnk == 'GET DATA BITS' : self.get_data_bits(owr)
193 else : raise Exception('Invalid state: %d' % self.state)
195 # Save current RX/TX values for the next round.