2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # Dict which maps command IDs to their names and descriptions.
25 0x06: ('WREN', 'Write enable'),
26 0x04: ('WRDI', 'Write disable'),
27 0x9f: ('RDID', 'Read identification'),
28 0x05: ('RDSR', 'Read status register'),
29 0x01: ('WRSR', 'Write status register'),
30 0x03: ('READ', 'Read data'),
31 0x0b: ('FAST/READ', 'Fast read data'),
32 0xbb: ('2READ', '2x I/O read'),
33 0x20: ('SE', 'Sector erase'),
34 0xd8: ('BE', 'Block erase'),
35 0x60: ('CE', 'Chip erase'),
36 0xc7: ('CE2', 'Chip erase'), # Alternative command ID
37 0x02: ('PP', 'Page program'),
38 0xad: ('CP', 'Continuously program mode'),
39 0xb9: ('DP', 'Deep power down'),
40 0xab: ('RDP/RES', 'Release from deep powerdown / Read electronic ID'),
41 0x90: ('REMS', 'Read electronic manufacturer & device ID'),
42 0xef: ('REMS2', 'Read ID for 2x I/O mode'),
43 0xb1: ('ENSO', 'Enter secured OTP'),
44 0xc1: ('EXSO', 'Exit secured OTP'),
45 0x2b: ('RDSCUR', 'Read security register'),
46 0x2f: ('WRSCUR', 'Write security register'),
47 0x70: ('ESRY', 'Enable SO to output RY/BY#'),
48 0x80: ('DSRY', 'Disable SO to output RY/BY#'),
57 def cmd_annotation_classes():
58 return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()])
60 def decode_status_reg(data):
61 # TODO: Additional per-bit(s) self.put() calls with correct start/end.
63 # Bits[0:0]: WIP (write in progress)
64 s = 'W' if (data & (1 << 0)) else 'No w'
65 ret = '%srite operation in progress.\n' % s
67 # Bits[1:1]: WEL (write enable latch)
68 s = '' if (data & (1 << 1)) else 'not '
69 ret += 'Internal write enable latch is %sset.\n' % s
71 # Bits[5:2]: Block protect bits
72 # TODO: More detailed decoding (chip-dependent).
73 ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)
75 # Bits[6:6]: Continuously program mode (CP mode)
76 s = '' if (data & (1 << 6)) else 'not '
77 ret += 'Device is %sin continuously program mode (CP mode).\n' % s
79 # Bits[7:7]: SRWD (status register write disable)
80 s = 'not ' if (data & (1 << 7)) else ''
81 ret += 'Status register writes are %sallowed.\n' % s
85 class Decoder(srd.Decoder):
89 longname = 'Macronix MX25Lxx05D'
90 desc = 'SPI (NOR) flash chip protocol.'
93 outputs = ['mx25lxx05d']
94 annotations = cmd_annotation_classes() + (
97 ('warnings', 'Warnings'),
100 ('bits', 'Bits', (24, 25)),
101 ('commands', 'Commands', tuple(range(23 + 1))),
102 ('warnings', 'Warnings', (26,)),
105 def __init__(self, **kwargs):
112 self.out_ann = self.register(srd.OUTPUT_ANN)
114 def putx(self, data):
115 # Simplification, most annotations span exactly one SPI byte/packet.
116 self.put(self.ss, self.es, self.out_ann, data)
118 def putb(self, data):
119 self.put(self.block_ss, self.block_es, self.out_ann, data)
121 def handle_wren(self, mosi, miso):
122 self.putx([0, ['Command: %s' % cmds[self.state][1]]])
125 def handle_wrdi(self, mosi, miso):
128 # TODO: Check/display device ID / name
129 def handle_rdid(self, mosi, miso):
130 if self.cmdstate == 1:
131 # Byte 1: Master sends command ID.
132 self.ss_block = self.ss
133 self.putx([2, ['Command: %s' % cmds[self.state][1]]])
134 elif self.cmdstate == 2:
135 # Byte 2: Slave sends the JEDEC manufacturer ID.
136 self.putx([2, ['Manufacturer ID: 0x%02x' % miso]])
137 elif self.cmdstate == 3:
138 # Byte 3: Slave sends the memory type (0x20 for this chip).
139 self.putx([2, ['Memory type: 0x%02x' % miso]])
140 elif self.cmdstate == 4:
141 # Byte 4: Slave sends the device ID.
142 self.device_id = miso
143 self.putx([2, ['Device ID: 0x%02x' % miso]])
145 if self.cmdstate == 4:
146 # TODO: Check self.device_id is valid & exists in device_names.
147 # TODO: Same device ID? Check!
148 d = 'Device: Macronix %s' % device_name[self.device_id]
149 self.put(self.ss_block, self.es, self.out_ann, [0, [d]])
154 def handle_rdsr(self, mosi, miso):
155 # Read status register: Master asserts CS#, sends RDSR command,
156 # reads status register byte. If CS# is kept asserted, the status
157 # register can be read continuously / multiple times in a row.
158 # When done, the master de-asserts CS# again.
159 if self.cmdstate == 1:
160 # Byte 1: Master sends command ID.
161 self.putx([3, ['Command: %s' % cmds[self.state][1]]])
162 elif self.cmdstate >= 2:
163 # Bytes 2-x: Slave sends status register as long as master clocks.
164 if self.cmdstate <= 3: # TODO: While CS# asserted.
165 self.putx([24, ['Status register: 0x%02x' % miso]])
166 self.putx([25, [decode_status_reg(miso)]])
168 if self.cmdstate == 3: # TODO: If CS# got de-asserted.
174 def handle_wrsr(self, mosi, miso):
177 def handle_read(self, mosi, miso):
178 # Read data bytes: Master asserts CS#, sends READ command, sends
179 # 3-byte address, reads >= 1 data bytes, de-asserts CS#.
180 if self.cmdstate == 1:
181 # Byte 1: Master sends command ID.
182 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
183 elif self.cmdstate in (2, 3, 4):
184 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
185 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
186 # self.putx([0, ['Read address, byte %d: 0x%02x' % \
187 # (4 - self.cmdstate, mosi)]])
188 if self.cmdstate == 4:
189 self.putx([24, ['Read address: 0x%06x' % self.addr]])
191 elif self.cmdstate >= 5:
192 # Bytes 5-x: Master reads data bytes (until CS# de-asserted).
193 # TODO: For now we hardcode 256 bytes per READ command.
194 if self.cmdstate <= 256 + 4: # TODO: While CS# asserted.
195 self.data.append(miso)
196 # self.putx([0, ['New read byte: 0x%02x' % miso]])
198 if self.cmdstate == 256 + 4: # TODO: If CS# got de-asserted.
199 # s = ', '.join(map(hex, self.data))
200 s = ''.join(map(chr, self.data))
201 self.putx([24, ['Read data']])
202 self.putx([25, ['Read data: %s' % s]])
209 def handle_fast_read(self, mosi, miso):
210 # Fast read: Master asserts CS#, sends FAST READ command, sends
211 # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#.
212 if self.cmdstate == 1:
213 # Byte 1: Master sends command ID.
214 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
215 elif self.cmdstate in (2, 3, 4):
216 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
217 self.putx([24, ['AD%d: 0x%02x' % (self.cmdstate - 1, mosi)]])
218 if self.cmdstate == 2:
219 self.block_ss = self.ss
220 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
221 elif self.cmdstate == 5:
222 self.putx([24, ['Dummy byte: 0x%02x' % mosi]])
223 self.block_es = self.es
224 self.putb([5, ['Read address: 0x%06x' % self.addr]])
226 elif self.cmdstate >= 6:
227 # Bytes 6-x: Master reads data bytes (until CS# de-asserted).
228 # TODO: For now we hardcode 32 bytes per FAST READ command.
229 if self.cmdstate == 6:
230 self.block_ss = self.ss
231 if self.cmdstate <= 32 + 5: # TODO: While CS# asserted.
232 self.data.append(miso)
233 if self.cmdstate == 32 + 5: # TODO: If CS# got de-asserted.
234 self.block_es = self.es
235 s = ' '.join([hex(b)[2:] for b in self.data])
236 self.putb([25, ['Read data: %s' % s]])
243 def handle_2read(self, mosi, miso):
246 # TODO: Warn/abort if we don't see the necessary amount of bytes.
247 # TODO: Warn if WREN was not seen before.
248 def handle_se(self, mosi, miso):
249 if self.cmdstate == 1:
250 # Byte 1: Master sends command ID.
252 self.ss_block = self.ss
253 self.putx([8, ['Command: %s' % cmds[self.state][1]]])
254 elif self.cmdstate in (2, 3, 4):
255 # Bytes 2/3/4: Master sends sectror address (24bits, MSB-first).
256 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
257 # self.putx([0, ['Sector address, byte %d: 0x%02x' % \
258 # (4 - self.cmdstate, mosi)]])
260 if self.cmdstate == 4:
261 d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
262 self.put(self.ss_block, self.es, self.out_ann, [24, [d]])
263 # TODO: Max. size depends on chip, check that too if possible.
264 if self.addr % 4096 != 0:
265 # Sector addresses must be 4K-aligned (same for all 3 chips).
266 d = 'Warning: Invalid sector address!'
267 self.put(self.ss_block, self.es, self.out_ann, [101, [d]])
272 def handle_be(self, mosi, miso):
275 def handle_ce(self, mosi, miso):
278 def handle_ce2(self, mosi, miso):
281 def handle_pp(self, mosi, miso):
282 # Page program: Master asserts CS#, sends PP command, sends 3-byte
283 # page address, sends >= 1 data bytes, de-asserts CS#.
284 if self.cmdstate == 1:
285 # Byte 1: Master sends command ID.
286 self.putx([12, ['Command: %s' % cmds[self.state][1]]])
287 elif self.cmdstate in (2, 3, 4):
288 # Bytes 2/3/4: Master sends page address (24bits, MSB-first).
289 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
290 # self.putx([0, ['Page address, byte %d: 0x%02x' % \
291 # (4 - self.cmdstate, mosi)]])
292 if self.cmdstate == 4:
293 self.putx([24, ['Page address: 0x%06x' % self.addr]])
295 elif self.cmdstate >= 5:
296 # Bytes 5-x: Master sends data bytes (until CS# de-asserted).
297 # TODO: For now we hardcode 256 bytes per page / PP command.
298 if self.cmdstate <= 256 + 4: # TODO: While CS# asserted.
299 self.data.append(mosi)
300 # self.putx([0, ['New data byte: 0x%02x' % mosi]])
302 if self.cmdstate == 256 + 4: # TODO: If CS# got de-asserted.
303 # s = ', '.join(map(hex, self.data))
304 s = ''.join(map(chr, self.data))
305 self.putx([24, ['Page data']])
306 self.putx([25, ['Page data: %s' % s]])
313 def handle_cp(self, mosi, miso):
316 def handle_dp(self, mosi, miso):
319 def handle_rdp_res(self, mosi, miso):
322 def handle_rems(self, mosi, miso):
323 if self.cmdstate == 1:
324 # Byte 1: Master sends command ID.
325 self.ss_block = self.ss
326 self.putx([16, ['Command: %s' % cmds[self.state][1]]])
327 elif self.cmdstate in (2, 3):
328 # Bytes 2/3: Master sends two dummy bytes.
329 # TODO: Check dummy bytes? Check reply from device?
330 self.putx([24, ['Dummy byte: %s' % mosi]])
331 elif self.cmdstate == 4:
332 # Byte 4: Master sends 0x00 or 0x01.
333 # 0x00: Master wants manufacturer ID as first reply byte.
334 # 0x01: Master wants device ID as first reply byte.
335 self.manufacturer_id_first = True if (mosi == 0x00) else False
336 d = 'manufacturer' if (mosi == 0x00) else 'device'
337 self.putx([24, ['Master wants %s ID first' % d]])
338 elif self.cmdstate == 5:
339 # Byte 5: Slave sends manufacturer ID (or device ID).
341 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
342 self.putx([24, ['%s ID' % d]])
343 elif self.cmdstate == 6:
344 # Byte 6: Slave sends device ID (or manufacturer ID).
345 self.ids.append(miso)
346 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
347 self.putx([24, ['%s ID' % d]])
349 if self.cmdstate == 6:
350 id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
351 self.putx([24, ['Device: Macronix %s' % device_name[id]]])
356 def handle_rems2(self, mosi, miso):
359 def handle_enso(self, mosi, miso):
362 def handle_exso(self, mosi, miso):
365 def handle_rdscur(self, mosi, miso):
368 def handle_wrscur(self, mosi, miso):
371 def handle_esry(self, mosi, miso):
374 def handle_dsry(self, mosi, miso):
377 def decode(self, ss, es, data):
379 ptype, mosi, miso = data
381 # if ptype == 'DATA':
382 # self.putx([0, ['MOSI: 0x%02x, MISO: 0x%02x' % (mosi, miso)]])
384 # if ptype == 'CS-CHANGE':
385 # if mosi == 1 and miso == 0:
386 # self.putx([0, ['Asserting CS#']])
387 # elif mosi == 0 and miso == 1:
388 # self.putx([0, ['De-asserting CS#']])
393 self.ss, self.es = ss, es
395 # If we encountered a known chip command, enter the resp. state.
396 if self.state is None:
401 if self.state in cmds:
402 s = 'handle_%s' % cmds[self.state][0].lower().replace('/', '_')
403 handle_reg = getattr(self, s)
404 handle_reg(mosi, miso)
406 self.putx([24, ['Unknown command: 0x%02x' % mosi]])