2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2016 Elias Oenal <sigrok@eliasoenal.com>
5 ## All rights reserved.
7 ## Redistribution and use in source and binary forms, with or without
8 ## modification, are permitted provided that the following conditions are met:
10 ## 1. Redistributions of source code must retain the above copyright notice,
11 ## this list of conditions and the following disclaimer.
12 ## 2. Redistributions in binary form must reproduce the above copyright notice,
13 ## this list of conditions and the following disclaimer in the documentation
14 ## and/or other materials provided with the distribution.
16 ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 ## POSSIBILITY OF SUCH DAMAGE.
29 import sigrokdecode as srd
31 class Decoder(srd.Decoder):
35 longname = 'Management Data Input/Output'
36 desc = 'Half-duplex sync serial bus for MII management between MAC and PHY.'
41 {'id': 'mdc', 'name': 'MDC', 'desc': 'Clock'},
42 {'id': 'mdio', 'name': 'MDIO', 'desc': 'Data'},
45 {'id': 'show_debug_bits', 'desc': 'Show debug bits',
46 'default': 'no', 'values': ('yes', 'no')},
49 ('bit-val', 'Bit value'),
50 ('bit-num', 'Bit number'),
52 ('frame-idle', 'Bus idle state'),
53 ('frame-error', 'Frame error'),
57 ('bit-val', 'Bit value', (0,)),
58 ('bit-num', 'Bit number', (1,)),
59 ('frame', 'Frame', (2, 3)),
60 ('frame-error', 'Frame error', (4,)),
61 ('decode', 'Decode', (5,)),
67 self.clause45_addr = -1 # Clause 45 is context sensitive.
68 self.reset_decoder_state()
71 self.out_python = self.register(srd.OUTPUT_PYTHON)
72 self.out_ann = self.register(srd.OUTPUT_ANN)
74 def putbit(self, mdio, ss, es):
75 self.put(ss, es, self.out_ann, [0, ['%d' % mdio]])
76 if self.options['show_debug_bits'] == 'yes':
77 self.put(ss, es, self.out_ann, [1, ['%d' % (self.bitcount - 1), '%d' % ((self.bitcount - 1) % 10)]])
79 def putff(self, data):
80 self.put(self.ss_frame_field, self.samplenum, self.out_ann, data)
83 self.put(self.ss_frame_field, self.mdiobits[0][2], self.out_ann,
84 [2, ['DATA: %04X' % self.data, 'DATA', 'D']])
86 if self.clause45 and self.opcode == 0:
87 self.clause45_addr = self.data
90 if self.opcode > 0 or not self.clause45:
92 if self.clause45 and self.clause45_addr != -1:
93 decoded_min += str.format('ADDR: %04X ' % self.clause45_addr)
95 decoded_min += str.format('ADDR: UKWN ' % self.clause45_addr)
97 if self.clause45 and self.opcode > 1 \
98 or (not self.clause45 and self.opcode):
99 decoded_min += str.format('READ: %04X' % self.data)
102 decoded_min += str.format('WRITE: %04X' % self.data)
104 decoded_ext = str.format(' %s: %02d' % \
105 ('PRTAD' if self.clause45 else 'PHYAD', self.portad))
106 decoded_ext += str.format(' %s: %02d' % \
107 ('DEVAD' if self.clause45 else 'REGAD', self.devad))
108 if self.ta_invalid or self.op_invalid:
109 decoded_ext += ' ERROR'
110 self.put(self.ss_frame, self.mdiobits[0][2], self.out_ann,
111 [5, [decoded_min + decoded_ext, decoded_min]])
113 self.put(self.ss_frame, self.mdiobits[0][2], self.out_python,
114 [(bool(self.clause45), int(self.clause45_addr), \
115 bool(is_read), int(self.portad), int(self.devad), \
118 # Post read increment address.
119 if self.clause45 and self.opcode == 2 and self.clause45_addr != -1:
120 self.clause45_addr += 1
122 def reset_decoder_state(self):
128 self.ss_frame_field = -1
129 self.preamble_len = 0
140 def state_PRE(self, mdio):
142 if mdio == 0: # Stay in illegal bus state.
144 else: # Leave and continue parsing.
146 self.put(self.ss_illegal, self.samplenum, self.out_ann,
147 [4, ['ILLEGAL BUS STATE', 'ILL']])
148 self.ss_frame = self.samplenum
150 if self.ss_frame == -1:
151 self.ss_frame = self.samplenum
154 self.preamble_len += 1
156 # Valid MDIO can't clock more than 16 succeeding ones without being
157 # in either IDLE or PRE.
158 if self.preamble_len > 16:
159 if self.preamble_len >= 10000 + 32:
160 self.put(self.ss_frame, self.mdiobits[32][1], self.out_ann,
161 [3, ['IDLE #%d' % (self.preamble_len - 32), 'IDLE', 'I']])
162 self.ss_frame = self.mdiobits[32][1]
163 self.preamble_len = 32
164 # This is getting out of hand, free some memory.
165 del self.mdiobits[33:-1]
167 if self.preamble_len < 32:
168 self.ss_frame = self.mdiobits[self.preamble_len][1]
169 self.put(self.ss_frame, self.samplenum, self.out_ann,
170 [4, ['SHORT PREAMBLE', 'SHRT PRE']])
171 elif self.preamble_len > 32:
172 self.ss_frame = self.mdiobits[32][1]
173 self.put(self.mdiobits[self.preamble_len][1],
174 self.mdiobits[32][1], self.out_ann,
175 [3, ['IDLE #%d' % (self.preamble_len - 32),
177 self.preamble_len = 32
179 self.ss_frame = self.mdiobits[32][1]
180 self.put(self.ss_frame, self.samplenum, self.out_ann,
181 [2, ['PRE #%d' % self.preamble_len, 'PRE', 'P']])
182 self.ss_frame_field = self.samplenum
185 self.ss_illegal = self.ss_frame
188 def state_ST(self, mdio):
193 def state_OP(self, mdio):
194 if self.opcode == -1:
196 st = ['ST (Clause 45)', 'ST 45']
198 st = ['ST (Clause 22)', 'ST 22']
199 self.putff([2, st + ['ST', 'S']])
200 self.ss_frame_field = self.samplenum
211 if mdio == self.opcode:
212 self.op_invalid = 'invalid for Clause 22'
215 def state_PRTAD(self, mdio):
216 if self.portad == -1:
220 op = ['OP: ADDR', 'OP: A']
221 elif self.opcode == 1:
222 op = ['OP: WRITE', 'OP: W']
223 elif self.opcode == 2:
224 op = ['OP: READINC', 'OP: RI']
225 elif self.opcode == 3:
226 op = ['OP: READ', 'OP: R']
228 op = ['OP: READ', 'OP: R'] if self.opcode else ['OP: WRITE', 'OP: W']
229 self.putff([2, op + ['OP', 'O']])
231 self.putff([4, ['OP %s' % self.op_invalid, 'OP', 'O']])
232 self.ss_frame_field = self.samplenum
233 self.portad_bits -= 1
234 self.portad |= mdio << self.portad_bits
235 if not self.portad_bits:
238 def state_DEVAD(self, mdio):
242 prtad = ['PRTAD: %02d' % self.portad, 'PRT', 'P']
244 prtad = ['PHYAD: %02d' % self.portad, 'PHY', 'P']
245 self.putff([2, prtad])
246 self.ss_frame_field = self.samplenum
248 self.devad |= mdio << self.devad_bits
249 if not self.devad_bits:
252 def state_TA(self, mdio):
253 if self.ta_invalid == -1:
256 regad = ['DEVAD: %02d' % self.devad, 'DEV', 'D']
258 regad = ['REGAD: %02d' % self.devad, 'REG', 'R']
259 self.putff([2, regad])
260 self.ss_frame_field = self.samplenum
261 if mdio != 1 and ((self.clause45 and self.opcode < 2)
262 or (not self.clause45 and self.opcode == 0)):
263 self.ta_invalid = ' invalid (bit1)'
267 self.ta_invalid = ' invalid (bit1 and bit2)'
269 self.ta_invalid = ' invalid (bit2)'
272 def state_DATA(self, mdio):
275 self.putff([2, ['TURNAROUND', 'TA', 'T']])
277 self.putff([4, ['TURNAROUND%s' % self.ta_invalid,
278 'TA%s' % self.ta_invalid, 'TA', 'T']])
279 self.ss_frame_field = self.samplenum
281 self.data |= mdio << self.data_bits
282 if not self.data_bits:
284 self.mdiobits[0][2] = self.mdiobits[0][1] + self.quartile_cycle_length()
286 self.putbit(self.mdiobits[0][0], self.mdiobits[0][1], self.mdiobits[0][2])
288 self.reset_decoder_state()
290 def process_state(self, argument, mdio):
291 method_name = 'state_' + str(argument)
292 method = getattr(self, method_name)
295 # Returns the first quartile point of the frames cycle lengths. This is a
296 # conservative guess for the end of the last cycle. On average it will be
297 # more likely to fall short, than being too long, which makes for better
298 # readability in GUIs.
299 def quartile_cycle_length(self):
300 # 48 is the minimum number of samples we have to have at the end of a
301 # frame. The last sample only has a leading clock edge and is ignored.
303 for i in range(1, 49):
304 bitlen.append(self.mdiobits[i][2] - self.mdiobits[i][1])
305 bitlen = sorted(bitlen)
308 def handle_bit(self, mdio):
310 self.mdiobits.insert(0, [mdio, self.samplenum, -1])
312 if self.bitcount > 0:
313 self.mdiobits[1][2] = self.samplenum # Note end of last cycle.
314 # Output the last bit we processed.
315 self.putbit(self.mdiobits[1][0], self.mdiobits[1][1], self.mdiobits[1][2])
317 self.process_state(self.state, mdio)
321 # Process pin state upon rising MDC edge.
322 pins = self.wait({0: 'r'})
323 self.handle_bit(pins[1])