2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
24 # START field (indicates start or stop of a transaction)
26 0b0000: 'Start of cycle for a target',
28 0b0010: 'Grant for bus master 0',
29 0b0011: 'Grant for bus master 1',
39 0b1101: 'Start of cycle for a Firmware Memory Read cycle',
40 0b1110: 'Start of cycle for a Firmware Memory Write cycle',
41 0b1111: 'Stop/abort (end of a cycle for a target)',
43 # Cycle type / direction field
44 # Bit 0 (LAD[0]) is unused, should always be 0.
45 # Neither host nor peripheral are allowed to drive 0b11x0.
49 0b0100: 'Memory read',
50 0b0110: 'Memory write',
53 0b1100: 'Reserved / not allowed',
54 0b1110: 'Reserved / not allowed',
56 # SIZE field (determines how many bytes are to be transferred)
57 # Bits[3:2] are reserved, must be driven to 0b00.
58 # Neither host nor peripheral are allowed to drive 0b0010.
60 0b0000: '8 bits (1 byte)',
61 0b0001: '16 bits (2 bytes)',
62 0b0010: 'Reserved / not allowed',
63 0b0011: '32 bits (4 bytes)',
65 # CHANNEL field (bits[2:0] contain the DMA channel number)
76 # SYNC field (used to add wait states)
87 0b1001: 'Ready more (DMA only)',
97 class Decoder(srd.Decoder):
101 longname = 'Low Pin Count'
102 desc = 'Protocol for low-bandwidth devices on PC mainboards.'
108 {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'},
109 {'id': 'lclk', 'name': 'LCLK', 'desc': 'Clock'},
110 {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'Addr/control/data 0'},
111 {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'Addr/control/data 1'},
112 {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'Addr/control/data 2'},
113 {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'Addr/control/data 3'},
115 optional_channels = (
116 {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'},
117 {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'Encoded DMA / bus master request'},
118 {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'Serialized IRQ'},
119 {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'Clock run'},
120 {'id': 'lpme', 'name': 'LPME#', 'desc': 'LPC power management event'},
121 {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'Power down'},
122 {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'System Management Interrupt'},
125 ('warnings', 'Warnings'),
127 ('cycle-type', 'Cycle-type/direction'),
129 ('tar1', 'Turn-around cycle 1'),
132 ('tar2', 'Turn-around cycle 2'),
135 ('data', 'Data', (1, 2, 3, 4, 5, 6, 7)),
136 ('warnings', 'Warnings', (0,)),
154 self.ss_block = self.es_block = None
157 self.out_ann = self.register(srd.OUTPUT_ANN)
159 def putb(self, data):
160 self.put(self.ss_block, self.es_block, self.out_ann, data)
162 def handle_get_start(self, lad, lad_bits, lframe):
163 # LAD[3:0]: START field (1 clock cycle).
165 # The last value of LAD[3:0] before LFRAME# gets de-asserted is what
166 # the peripherals must use. However, the host can keep LFRAME# asserted
167 # multiple clocks, and we output all START fields that occur, even
168 # though the peripherals are supposed to ignore all but the last one.
169 self.es_block = self.samplenum
170 self.putb([1, [fields['START'][lad], 'START', 'St', 'S']])
171 self.ss_block = self.samplenum
173 # Output a warning if LAD[3:0] changes while LFRAME# is low.
175 if (self.lad != -1 and self.lad != lad):
176 self.putb([0, ['LAD[3:0] changed while LFRAME# was asserted']])
178 # LFRAME# is asserted (low). Wait until it gets de-asserted again
179 # (the host is allowed to keep it asserted multiple clocks).
183 self.start_field = self.lad
184 self.state = 'GET CT/DR'
186 def handle_get_ct_dr(self, lad, lad_bits):
187 # LAD[3:0]: Cycle type / direction field (1 clock cycle).
189 self.cycle_type = fields['CT_DR'].get(lad, 'Reserved / unknown')
191 # TODO: Warning/error on invalid cycle types.
192 if 'Reserved' in self.cycle_type:
193 self.putb([0, ['Invalid cycle type (%s)' % lad_bits]])
195 self.es_block = self.samplenum
196 self.putb([2, ['Cycle type: %s' % self.cycle_type]])
197 self.ss_block = self.samplenum
199 self.state = 'GET ADDR'
203 def handle_get_addr(self, lad, lad_bits):
204 # LAD[3:0]: ADDR field (4/8/0 clock cycles).
206 # I/O cycles: 4 ADDR clocks. Memory cycles: 8 ADDR clocks.
207 # DMA cycles: no ADDR clocks at all.
208 if self.cycle_type in ('I/O read', 'I/O write'):
209 addr_nibbles = 4 # Address is 16bits.
210 elif self.cycle_type in ('Memory read', 'Memory write'):
211 addr_nibbles = 8 # Address is 32bits.
213 addr_nibbles = 0 # TODO: How to handle later on?
215 # Addresses are driven MSN-first.
216 offset = ((addr_nibbles - 1) - self.cur_nibble) * 4
217 self.addr |= (lad << offset)
219 # Continue if we haven't seen all ADDR cycles, yet.
220 if (self.cur_nibble < addr_nibbles - 1):
224 self.es_block = self.samplenum
225 s = 'Address: 0x%%0%dx' % addr_nibbles
226 self.putb([3, [s % self.addr]])
227 self.ss_block = self.samplenum
229 self.state = 'GET TAR'
232 def handle_get_tar(self, lad, lad_bits):
233 # LAD[3:0]: First TAR (turn-around) field (2 clock cycles).
235 self.es_block = self.samplenum
236 self.putb([4, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
237 self.ss_block = self.samplenum
239 # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
240 # either the host or peripheral. On the second clock cycle,
241 # the host or peripheral tri-states LAD[3:0], but its value
242 # should still be 1111, due to pull-ups on the LAD lines.
243 if lad_bits != '1111':
244 self.putb([0, ['TAR, cycle %d: %s (expected 1111)' % \
245 (self.tarcount, lad_bits)]])
247 if (self.tarcount != 1):
252 self.state = 'GET SYNC'
254 def handle_get_sync(self, lad, lad_bits):
255 # LAD[3:0]: SYNC field (1-n clock cycles).
257 self.sync_val = lad_bits
258 self.cycle_type = fields['SYNC'].get(lad, 'Reserved / unknown')
260 # TODO: Warnings if reserved value are seen?
261 if 'Reserved' in self.cycle_type:
262 self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \
263 (self.synccount, self.sync_val)]])
265 self.es_block = self.samplenum
266 self.putb([5, ['SYNC, cycle %d: %s' % (self.synccount, self.sync_val)]])
267 self.ss_block = self.samplenum
272 self.state = 'GET DATA'
274 def handle_get_data(self, lad, lad_bits):
275 # LAD[3:0]: DATA field (2 clock cycles).
277 # Data is driven LSN-first.
278 if (self.cycle_count == 0):
280 elif (self.cycle_count == 1):
281 self.databyte |= (lad << 4)
283 raise Exception('Invalid cycle_count: %d' % self.cycle_count)
285 if (self.cycle_count != 1):
286 self.cycle_count += 1
289 self.es_block = self.samplenum
290 self.putb([6, ['DATA: 0x%02x' % self.databyte]])
291 self.ss_block = self.samplenum
294 self.state = 'GET TAR2'
296 def handle_get_tar2(self, lad, lad_bits):
297 # LAD[3:0]: Second TAR field (2 clock cycles).
299 self.es_block = self.samplenum
300 self.putb([7, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
301 self.ss_block = self.samplenum
303 # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
304 # either the host or peripheral. On the second clock cycle,
305 # the host or peripheral tri-states LAD[3:0], but its value
306 # should still be 1111, due to pull-ups on the LAD lines.
307 if lad_bits != '1111':
308 self.putb([0, ['Warning: TAR, cycle %d: %s (expected 1111)'
309 % (self.tarcount, lad_bits)]])
311 if (self.tarcount != 1):
320 # TODO: Come up with more appropriate self.wait() conditions.
323 # If none of the pins changed, there's nothing to do.
324 if self.oldpins == pins:
327 # Store current pin values for the next round.
330 # Get individual pin values into local variables.
331 (lframe, lclk, lad0, lad1, lad2, lad3) = pins[:6]
332 (lreset, ldrq, serirq, clkrun, lpme, lpcpd, lsmi) = pins[6:]
334 # Only look at the signals upon rising LCLK edges. The LPC clock
335 # is the same as the PCI clock (which is sampled at rising edges).
336 if not (self.oldlclk == 0 and lclk == 1):
340 # Store LAD[3:0] bit values (one nibble) in local variables.
341 # Most (but not all) states need this.
342 if self.state != 'IDLE':
343 lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0
344 lad_bits = '{:04b}'.format(lad)
345 # self.putb([0, ['LAD: %s' % lad_bits]])
347 # TODO: Only memory read/write is currently supported/tested.
350 if self.state == 'IDLE':
351 # A valid LPC cycle starts with LFRAME# being asserted (low).
354 self.ss_block = self.samplenum
355 self.state = 'GET START'
357 elif self.state == 'GET START':
358 self.handle_get_start(lad, lad_bits, lframe)
359 elif self.state == 'GET CT/DR':
360 self.handle_get_ct_dr(lad, lad_bits)
361 elif self.state == 'GET ADDR':
362 self.handle_get_addr(lad, lad_bits)
363 elif self.state == 'GET TAR':
364 self.handle_get_tar(lad, lad_bits)
365 elif self.state == 'GET SYNC':
366 self.handle_get_sync(lad, lad_bits)
367 elif self.state == 'GET DATA':
368 self.handle_get_data(lad, lad_bits)
369 elif self.state == 'GET TAR2':
370 self.handle_get_tar2(lad, lad_bits)