2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
24 # Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs),
25 # as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions.
26 # Instead, BYPASS is decoded for any of these instructions.
28 '1111': ['BYPASS', 1], # Bypass register
29 '1110': ['IDCODE', 32], # ID code register
30 '1010': ['DPACC', 35], # Debug port access register
31 '1011': ['APACC', 35], # Access port access register
32 '1000': ['ABORT', 35], # Abort register # TODO: 32 bits? Datasheet typo?
35 # ARM Cortex-M3 r1p1-01rel0 ID code
36 cm3_idcode = 0x3ba00477
38 # JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
40 0x06412041: 'Low-density device, rev. A',
41 0x06410041: 'Medium-density device, rev. A',
42 0x16410041: 'Medium-density device, rev. B/Z/Y',
43 0x06414041: 'High-density device, rev. A/Z/Y',
44 0x06430041: 'XL-density device, rev. A',
45 0x06418041: 'Connectivity-line device, rev. A/Z',
48 # ACK[2:0] in the DPACC/APACC registers (unlisted values are reserved)
54 # 32bit debug port registers (addressed via A[3:2])
56 '00': 'Reserved', # Must be kept at reset value
62 # APB-AP registers (each of them 32 bits wide)
64 0x00: ['CSW', 'Control/status word'],
65 0x04: ['TAR', 'Transfer address'],
67 0x0c: ['DRW', 'Data read/write'],
68 0x10: ['BD0', 'Banked data 0'],
69 0x14: ['BD1', 'Banked data 1'],
70 0x18: ['BD2', 'Banked data 2'],
71 0x1c: ['BD3', 'Banked data 3'],
72 # 0x20-0xf4: Reserved SBZ
73 0x800000000: ['ROM', 'Debug ROM address'],
74 0xfc: ['IDR', 'Identification register'],
77 # TODO: Split off generic ARM/Cortex-M3 parts into another protocol decoder?
79 # Bits[31:28]: Version (here: 0x3)
80 # JTAG-DP: 0x3, SW-DP: 0x2
81 # Bits[27:12]: Part number (here: 0xba00)
82 # JTAG-DP: 0xba00, SW-DP: 0xba10
83 # Bits[11:1]: JEDEC (JEP-106) manufacturer ID (here: 0x23b)
84 # Bits[11:8]: Continuation code ('ARM Limited': 0x04)
85 # Bits[7:1]: Identity code ('ARM Limited': 0x3b)
86 # Bits[0:0]: Reserved (here: 0x1)
87 def decode_device_id_code(bits):
88 id_hex = '0x%x' % int('0b' + bits, 2)
89 ver = '0x%x' % int('0b' + bits[-32:-28], 2)
90 part = '0x%x' % int('0b' + bits[-28:-12], 2)
91 manuf = '0x%x' % int('0b' + bits[-12:-1], 2)
92 res = '0x%x' % int('0b' + bits[-1], 2)
93 return (id_hex, ver, part, manuf, res)
95 # DPACC is used to access debug port registers (CTRL/STAT, SELECT, RDBUFF).
96 # APACC is used to access all Access Port (AHB-AP) registers.
98 # APACC/DPACC, when transferring data IN:
99 # Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
100 # Bits[2:1] = A[3:2]: 2-bit address (debug/access port register)
101 # Bits[0:0] = RnW: Read request (1) or write request (0)
102 def data_in(instruction, bits):
103 data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
104 data_hex = '0x%x' % int('0b' + data, 2)
105 r = 'Read request' if (rnw == '1') else 'Write request'
106 # reg = dp_reg[a] if (instruction == 'DPACC') else apb_ap_reg[a]
107 reg = dp_reg[a] if (instruction == 'DPACC') else a # TODO
108 return 'New transaction: DATA: %s, A: %s, RnW: %s' % (data_hex, reg, r)
110 # APACC/DPACC, when transferring data OUT:
111 # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
112 # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
114 data, ack = bits[:-3], bits[-3:]
115 data_hex = '0x%x' % int('0b' + data, 2)
116 ack_meaning = ack_val.get(ack, 'Reserved')
117 return 'Previous transaction result: DATA: %s, ACK: %s' \
118 % (data_hex, ack_meaning)
120 class Decoder(srd.Decoder):
123 name = 'JTAG / STM32'
124 longname = 'Joint Test Action Group / ST STM32'
125 desc = 'ST STM32-specific JTAG protocol.'
128 outputs = ['jtag_stm32']
130 ('text', 'Human-readable text'),
133 def __init__(self, **kwargs):
135 self.samplenums = None
138 self.out_ann = self.register(srd.OUTPUT_ANN)
140 def putx(self, data):
141 self.put(self.ss, self.es, self.out_ann, data)
143 def handle_reg_bypass(self, cmd, bits):
144 self.putx([0, ['BYPASS: ' + bits]])
146 def handle_reg_idcode(self, cmd, bits):
147 # IDCODE is a read-only register which is always accessible.
148 # IR == IDCODE: The device ID code is shifted out via DR next.
149 self.putx([0, ['IDCODE: %s (ver=%s, part=%s, manuf=%s, res=%s)' % \
150 decode_device_id_code(bits)]])
152 def handle_reg_dpacc(self, cmd, bits):
153 s = data_in('DPACC', bits) if (cmd == 'DR TDI') else data_out(bits)
156 def handle_reg_apacc(self, cmd, bits):
157 s = data_in('APACC', bits) if (cmd == 'DR TDI') else data_out(bits)
160 def handle_reg_abort(self, cmd, bits):
161 # Bits[31:1]: reserved. Bit[0]: DAPABORT.
162 a = '' if (bits[0] == '1') else 'No '
163 s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
166 # Warn if DAPABORT[31:1] contains non-zero bits.
167 if (bits[:-1] != ('0' * 31)):
168 self.putx([0, ['WARNING: DAPABORT[31:1] reserved!']])
170 def handle_reg_unknown(self, cmd, bits):
171 self.putx([0, ['Unknown instruction: %s' % bits]])
173 def decode(self, ss, es, data):
176 self.ss, self.es = ss, es
178 if cmd != 'NEW STATE':
179 val, self.samplenums = val
181 # The right-most char in the 'val' bitstring is the LSB.
183 # The STM32F10xxx has two serially connected JTAG TAPs, the
184 # boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits).
185 # See UM 31.5 "STM32F10xxx JTAG TAP connection" for details.
186 # Due to this, we need to ignore the last bit of each data shift.
190 if self.state == 'IDLE':
191 # Wait until a new instruction is shifted into the IR register.
194 # Switch to the state named after the instruction, or 'UNKNOWN'.
195 # The STM32F10xxx has two serially connected JTAG TAPs, the
196 # boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits).
197 # See UM 31.5 "STM32F10xxx JTAG TAP connection" for details.
198 # Currently we only care about the latter and use IR[3:0].
199 self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0]
200 self.putx([0, ['IR: ' + self.state]])
201 elif self.state == 'BYPASS':
202 # Here we're interested in incoming bits (TDI).
205 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
208 elif self.state in ('IDCODE', 'ABORT', 'UNKNOWN'):
209 # Here we're interested in outgoing bits (TDO).
212 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
215 elif self.state in ('DPACC', 'APACC'):
216 # Here we're interested in incoming and outgoing bits (TDI/TDO).
217 if cmd not in ('DR TDI', 'DR TDO'):
219 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
221 if cmd == 'DR TDO': # Assumes 'DR TDI' comes before 'DR TDO'.